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From: Vignesh Raghavendra <vigneshr@ti.com>
To: Jit Loon Lim <jit.loon.lim@intel.com>, <u-boot@lists.denx.de>
Cc: Jagan Teki <jagan@amarulasolutions.com>, Marek <marex@denx.de>,
	Simon <simon.k.r.goldschmidt@gmail.com>,
	Tien Fong <tien.fong.chee@intel.com>,
	Kok Kiang <kok.kiang.hea@intel.com>,
	Siew Chin <elly.siew.chin.lim@intel.com>,
	Sin Hui <sin.hui.kho@intel.com>, Raaj <raaj.lokanathan@intel.com>,
	Dinesh <dinesh.maniyam@intel.com>,
	Boon Khai <boon.khai.ng@intel.com>,
	Alif <alif.zakuan.yuslaimi@intel.com>,
	Teik Heng <teik.heng.chong@intel.com>,
	Hazim <muhammad.hazim.izzat.zamri@intel.com>,
	Chee Hong Ang <chee.hong.ang@intel.com>
Subject: Re: [PATCH 016/347] FogBugz #516535: Fix QSPI write issues
Date: Tue, 25 Oct 2022 11:38:12 +0530	[thread overview]
Message-ID: <fc5f3411-933e-eb3d-2eab-27060a3b779a@ti.com> (raw)
In-Reply-To: <20220830062009.24408-1-jit.loon.lim@intel.com>

Hi,

On 30/08/22 11:50 am, Jit Loon Lim wrote:
> From: Chee Hong Ang <chee.hong.ang@intel.com>
> 
> QSPI driver perform chip select on every flash read/write
> access. The driver need to disable/enable the QSPI controller
> while performing chip select. This may cause some data lost
> especially the QSPI controller is configured to run at slower
> speed as it may take longer time to access the flash device.
> This patch prevent the driver from disable/enable the QSPI
> controller too soon and inadvertently halting any ongoing flash
> read/write access by ensuring the QSPI controller is always in
> idle mode after each read/write access.
> 
> Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
> ---
>  drivers/spi/cadence_qspi_apb.c | 15 ++++++++-------
>  1 file changed, 8 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c
> index 2cdf4c9c9f..5e03495f45 100644
> --- a/drivers/spi/cadence_qspi_apb.c
> +++ b/drivers/spi/cadence_qspi_apb.c
> @@ -858,13 +858,9 @@ cadence_qspi_apb_indirect_read_execute(struct cadence_spi_plat *plat,
>  	writel(CQSPI_REG_INDIRECTRD_DONE,
>  	       plat->regbase + CQSPI_REG_INDIRECTRD);
>  
> -	/* Check indirect done status */
> -	ret = wait_for_bit_le32(plat->regbase + CQSPI_REG_INDIRECTRD,
> -				CQSPI_REG_INDIRECTRD_DONE, 0, 10, 0);
> -	if (ret) {
> -		printf("Indirect read clear completion error (%i)\n", ret);
> -		goto failrd;
> -	}

Why would you drop looking at CQSPI_REG_INDIRECTRD_DONE status bit? This
gives out a much granular error wrt what operation actually failed.


> +	/* Wait til QSPI is idle */
> +	if (!cadence_qspi_wait_idle(plat->regbase))
> +		return -EIO;
>  
>  	return 0;
>  
> @@ -1031,6 +1027,11 @@ cadence_qspi_apb_indirect_write_execute(struct cadence_spi_plat *plat,
>  
>  	if (bounce_buf)
>  		free(bounce_buf);
> +
> +	/* Wait til QSPI is idle */
> +	if (!cadence_qspi_wait_idle(plat->regbase))
> +		return -EIO;
> +
>  	return 0;
>  
>  failwr:

  parent reply	other threads:[~2022-10-25  6:08 UTC|newest]

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-08-30  6:20 [PATCH 016/347] FogBugz #516535: Fix QSPI write issues Jit Loon Lim
2022-10-23  5:33 ` Jagan Teki
2022-10-25  6:08 ` Vignesh Raghavendra [this message]
  -- strict thread matches above, loose matches on Subject: below --
2022-08-02 13:54 Jit Loon Lim
2022-08-09  2:57 ` Chee, Tien Fong

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