From mboxrd@z Thu Jan 1 00:00:00 1970 From: vijay.kilari@gmail.com Subject: [PATCH v5 15/22] xen/arm: ITS: implement hw_irq_controller for LPIs Date: Mon, 27 Jul 2015 16:41:57 +0530 Message-ID: <1437995524-19772-16-git-send-email-vijay.kilari@gmail.com> References: <1437995524-19772-1-git-send-email-vijay.kilari@gmail.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <1437995524-19772-1-git-send-email-vijay.kilari@gmail.com> List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org To: Ian.Campbell@citrix.com, julien.grall@citrix.com, stefano.stabellini@eu.citrix.com, stefano.stabellini@citrix.com, tim@xen.org, xen-devel@lists.xen.org Cc: Prasun.Kapoor@caviumnetworks.com, manish.jaggi@caviumnetworks.com, Vijaya Kumar K , vijay.kilari@gmail.com List-Id: xen-devel@lists.xenproject.org From: Vijaya Kumar K Implements hw_irq_controller api's required to handle LPI's Signed-off-by: Vijaya Kumar K --- v5: - Fixed review comments - Exposed gicv3_[host|guest]_irq_end and hook to its v4: - Implement separate hw_irq_controller for LPIs - Drop setting LPI affinity - virq and vid are moved under union - Introduced inv command handling - its_device is stored in irq_desc --- xen/arch/arm/gic-hip04.c | 14 ++++- xen/arch/arm/gic-v2.c | 14 ++++- xen/arch/arm/gic-v3-its.c | 124 ++++++++++++++++++++++++++++++++++++++++- xen/arch/arm/gic-v3.c | 33 +++++++++-- xen/arch/arm/gic.c | 14 ++++- xen/arch/arm/irq.c | 46 +++++++++++++++ xen/include/asm-arm/gic-its.h | 2 + xen/include/asm-arm/gic.h | 13 ++++- xen/include/asm-arm/irq.h | 15 ++++- 9 files changed, 258 insertions(+), 17 deletions(-) diff --git a/xen/arch/arm/gic-hip04.c b/xen/arch/arm/gic-hip04.c index fdd428a..9ad8b6a 100644 --- a/xen/arch/arm/gic-hip04.c +++ b/xen/arch/arm/gic-hip04.c @@ -634,6 +634,16 @@ static hw_irq_controller hip04gic_guest_irq_type = { .set_affinity = hip04gic_irq_set_affinity, }; +static hw_irq_controller *hip04gic_get_host_irq_type(unsigned int irq) +{ + return &hip04gic_host_irq_type; +} + +static hw_irq_controller *hip04gic_get_guest_irq_type(unsigned int irq) +{ + return &hip04gic_guest_irq_type; +} + static int __init hip04gic_init(void) { int res; @@ -716,8 +726,8 @@ const static struct gic_hw_operations hip04gic_ops = { .save_state = hip04gic_save_state, .restore_state = hip04gic_restore_state, .dump_state = hip04gic_dump_state, - .gic_host_irq_type = &hip04gic_host_irq_type, - .gic_guest_irq_type = &hip04gic_guest_irq_type, + .gic_get_host_irq_type = hip04gic_get_host_irq_type, + .gic_get_guest_irq_type = hip04gic_get_guest_irq_type, .eoi_irq = hip04gic_eoi_irq, .deactivate_irq = hip04gic_dir_irq, .read_irq = hip04gic_read_irq, diff --git a/xen/arch/arm/gic-v2.c b/xen/arch/arm/gic-v2.c index 5cc2bca..5c580bc 100644 --- a/xen/arch/arm/gic-v2.c +++ b/xen/arch/arm/gic-v2.c @@ -620,6 +620,16 @@ static hw_irq_controller gicv2_guest_irq_type = { .set_affinity = gicv2_irq_set_affinity, }; +static hw_irq_controller *gicv2_get_host_irq_type(unsigned int irq) +{ + return &gicv2_host_irq_type; +} + +static hw_irq_controller *gicv2_get_guest_irq_type(unsigned int irq) +{ + return &gicv2_guest_irq_type; +} + static int __init gicv2_init(void) { int res; @@ -702,8 +712,8 @@ const static struct gic_hw_operations gicv2_ops = { .save_state = gicv2_save_state, .restore_state = gicv2_restore_state, .dump_state = gicv2_dump_state, - .gic_host_irq_type = &gicv2_host_irq_type, - .gic_guest_irq_type = &gicv2_guest_irq_type, + .gic_get_host_irq_type = gicv2_get_host_irq_type, + .gic_get_guest_irq_type = gicv2_get_guest_irq_type, .eoi_irq = gicv2_eoi_irq, .deactivate_irq = gicv2_dir_irq, .read_irq = gicv2_read_irq, diff --git a/xen/arch/arm/gic-v3-its.c b/xen/arch/arm/gic-v3-its.c index 0d17885..5ffd52f 100644 --- a/xen/arch/arm/gic-v3-its.c +++ b/xen/arch/arm/gic-v3-its.c @@ -301,8 +301,8 @@ post: its_wait_for_range_completion(its, cmd, next_cmd); } -void its_send_inv(struct its_device *dev, struct its_collection *col, - u32 event_id) +static void its_send_inv(struct its_device *dev, struct its_collection *col, + u32 event_id) { its_cmd_block cmd; @@ -390,6 +390,126 @@ void its_send_discard(struct its_device *dev, struct its_collection *col, its_send_single_command(dev->its, &cmd, col); } +static void its_flush_and_invalidate_prop(struct irq_desc *desc, u8 *cfg) +{ + struct its_collection *col; + struct its_device *its_dev = get_irq_its_device(desc); + u32 vid = irq_to_vid(desc); + u16 col_id; + + ASSERT(vid < its_dev->nr_lpis); + + /* + * Make the above write visible to the redistributors. + * And yes, we're flushing exactly: One. Single. Byte. + * Humpf... + */ + if ( gic_rdists->flags & RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING ) + clean_and_invalidate_dcache_va_range(cfg, sizeof(*cfg)); + else + dsb(ishst); + + /* Get collection id for this event id */ + col_id = irqdesc_get_collection(desc); + col = &its_dev->its->collections[col_id]; + its_send_inv(its_dev, col, vid); +} + +static void its_set_lpi_state(struct irq_desc *desc, int enable) +{ + u8 *cfg; + + ASSERT(spin_is_locked(&its_lock)); + + cfg = gic_rdists->prop_page + desc->irq - FIRST_GIC_LPI; + if ( enable ) + *cfg |= LPI_PROP_ENABLED; + else + *cfg &= ~LPI_PROP_ENABLED; + + its_flush_and_invalidate_prop(desc, cfg); +} + +static void its_irq_enable(struct irq_desc *desc) +{ + unsigned long flags; + + ASSERT(spin_is_locked(&desc->lock)); + + spin_lock_irqsave(&its_lock, flags); + clear_bit(_IRQ_DISABLED, &desc->status); + dsb(sy); + its_set_lpi_state(desc, 1); + spin_unlock_irqrestore(&its_lock, flags); +} + +static void its_irq_disable(struct irq_desc *desc) +{ + unsigned long flags; + + ASSERT(spin_is_locked(&desc->lock)); + + spin_lock_irqsave(&its_lock, flags); + its_set_lpi_state(desc, 0); + set_bit(_IRQ_DISABLED, &desc->status); + spin_unlock_irqrestore(&its_lock, flags); +} + +static unsigned int its_irq_startup(struct irq_desc *desc) +{ + its_irq_enable(desc); + + return 0; +} + +static void its_irq_shutdown(struct irq_desc *desc) +{ + its_irq_disable(desc); +} + +static void its_irq_ack(struct irq_desc *desc) +{ + /* No ACK -- reading IAR has done this for us */ +} + +static void its_irq_set_affinity(struct irq_desc *desc, const cpumask_t *mask) +{ + /*TODO: Yet to support */ + return; +} + +static const hw_irq_controller its_host_lpi_type = { + .typename = "gic-its", + .startup = its_irq_startup, + .shutdown = its_irq_shutdown, + .enable = its_irq_enable, + .disable = its_irq_disable, + .ack = its_irq_ack, + .end = gicv3_host_irq_end, + .set_affinity = its_irq_set_affinity, +}; + +static const hw_irq_controller its_guest_lpi_type = { + .typename = "gic-its", + .startup = its_irq_startup, + .shutdown = its_irq_shutdown, + .enable = its_irq_enable, + .disable = its_irq_disable, + .ack = its_irq_ack, + .end = gicv3_guest_irq_end, + .set_affinity = its_irq_set_affinity, +}; + +hw_irq_controller *its_get_host_lpi_type(void) +{ + return &its_host_lpi_type; +} + +hw_irq_controller *its_get_guest_lpi_type(void) +{ + return &its_guest_lpi_type; +} + /* * How we allocate LPIs: * diff --git a/xen/arch/arm/gic-v3.c b/xen/arch/arm/gic-v3.c index 98d45bc..58e878e 100644 --- a/xen/arch/arm/gic-v3.c +++ b/xen/arch/arm/gic-v3.c @@ -40,6 +40,7 @@ #include #include #include +#include #include /* Global state */ @@ -1033,15 +1034,19 @@ static void gicv3_irq_ack(struct irq_desc *desc) /* No ACK -- reading IAR has done this for us */ } -static void gicv3_host_irq_end(struct irq_desc *desc) +void gicv3_host_irq_end(struct irq_desc *desc) { /* Lower the priority */ gicv3_eoi_irq(desc); - /* Deactivate */ - gicv3_dir_irq(desc); + /* + * LPIs does not have active state. Do do not deactivate, + * when EOI mode is set to 1. + */ + if ( !gic_is_lpi(desc->irq) ) + gicv3_dir_irq(desc); } -static void gicv3_guest_irq_end(struct irq_desc *desc) +void gicv3_guest_irq_end(struct irq_desc *desc) { /* Lower the priority of the IRQ */ gicv3_eoi_irq(desc); @@ -1146,6 +1151,22 @@ static const hw_irq_controller gicv3_guest_irq_type = { .set_affinity = gicv3_irq_set_affinity, }; +static hw_irq_controller *gicv3_get_host_irq_type(unsigned int irq) +{ + if ( gic_is_lpi(irq) ) + return its_get_host_lpi_type(); + + return &gicv3_host_irq_type; +} + +static hw_irq_controller *gicv3_get_guest_irq_type(unsigned int irq) +{ + if ( gic_is_lpi(irq) ) + return its_get_guest_lpi_type(); + + return &gicv3_guest_irq_type; +} + static int __init cmp_rdist(const void *a, const void *b) { const struct rdist_region *l = a, *r = a; @@ -1310,8 +1331,8 @@ static const struct gic_hw_operations gicv3_ops = { .save_state = gicv3_save_state, .restore_state = gicv3_restore_state, .dump_state = gicv3_dump_state, - .gic_host_irq_type = &gicv3_host_irq_type, - .gic_guest_irq_type = &gicv3_guest_irq_type, + .gic_get_host_irq_type = gicv3_get_host_irq_type, + .gic_get_guest_irq_type = gicv3_get_guest_irq_type, .eoi_irq = gicv3_eoi_irq, .deactivate_irq = gicv3_dir_irq, .read_irq = gicv3_read_irq, diff --git a/xen/arch/arm/gic.c b/xen/arch/arm/gic.c index cb4cdc8..092087d 100644 --- a/xen/arch/arm/gic.c +++ b/xen/arch/arm/gic.c @@ -104,6 +104,16 @@ void gic_restore_state(struct vcpu *v) gic_restore_pending_irqs(v); } +static inline hw_irq_controller *get_host_hw_irq_controller(unsigned int irq) +{ + return gic_hw_ops->gic_get_host_irq_type(irq); +} + +static inline hw_irq_controller *get_guest_hw_irq_controller(unsigned int irq) +{ + return gic_hw_ops->gic_get_guest_irq_type(irq); +} + /* * needs to be called with a valid cpu_mask, ie each cpu in the mask has * already called gic_cpu_init @@ -128,7 +138,7 @@ void gic_route_irq_to_xen(struct irq_desc *desc, const cpumask_t *cpu_mask, ASSERT(test_bit(_IRQ_DISABLED, &desc->status)); ASSERT(spin_is_locked(&desc->lock)); - desc->handler = gic_hw_ops->gic_host_irq_type; + desc->handler = get_host_hw_irq_controller(desc->irq); gic_set_irq_properties(desc, cpu_mask, priority); } @@ -159,7 +169,7 @@ int gic_route_irq_to_guest(struct domain *d, unsigned int virq, test_bit(GIC_IRQ_GUEST_ENABLED, &p->status) ) goto out; - desc->handler = gic_hw_ops->gic_guest_irq_type; + desc->handler = get_guest_hw_irq_controller(desc->irq); set_bit(_IRQ_GUEST, &desc->status); gic_set_irq_properties(desc, cpumask_of(v_target->processor), priority); diff --git a/xen/arch/arm/irq.c b/xen/arch/arm/irq.c index 63feb43..ccbe088 100644 --- a/xen/arch/arm/irq.c +++ b/xen/arch/arm/irq.c @@ -156,6 +156,52 @@ static inline struct domain *irq_get_domain(struct irq_desc *desc) return irq_get_guest_info(desc)->d; } +unsigned int irq_to_virq(struct irq_desc *desc) +{ + return irq_get_guest_info(desc)->virq; +} + +#ifdef HAS_GICV3 +unsigned int irq_to_vid(struct irq_desc *desc) +{ + ASSERT(desc->msi_desc != NULL); + + return desc->msi_desc->eventID; +} + +struct its_device *get_irq_its_device(struct irq_desc *desc) +{ + ASSERT(spin_is_locked(&desc->lock)); + ASSERT(desc->msi_desc != NULL); + + return desc->msi_desc->dev; +} + +void set_irq_its_device(struct irq_desc *desc, struct its_device *dev) +{ + ASSERT(spin_is_locked(&desc->lock)); + ASSERT(desc->msi_desc != NULL); + + desc->msi_desc->dev = dev; +} + +u16 irqdesc_get_collection(struct irq_desc *desc) +{ + ASSERT(spin_is_locked(&desc->lock)); + ASSERT(desc->msi_desc != NULL); + + return desc->msi_desc->col_id; +} + +void irqdesc_set_collection(struct irq_desc *desc, uint16_t col_id) +{ + ASSERT(spin_is_locked(&desc->lock)); + ASSERT(desc->msi_desc != NULL); + + desc->msi_desc->col_id = col_id; +} +#endif + void irq_set_affinity(struct irq_desc *desc, const cpumask_t *cpu_mask) { if ( desc != NULL ) diff --git a/xen/include/asm-arm/gic-its.h b/xen/include/asm-arm/gic-its.h index 7bb645e..110516a 100644 --- a/xen/include/asm-arm/gic-its.h +++ b/xen/include/asm-arm/gic-its.h @@ -354,6 +354,8 @@ struct gic_its_info { }; bool_t is_domain_lpi(struct domain *d, unsigned int lpi); +hw_irq_controller *its_get_host_lpi_type(void); +hw_irq_controller *its_get_guest_lpi_type(void); int its_init(struct rdist_prop *rdists); int its_cpu_init(void); int vits_get_vitt_entry(struct domain *d, uint32_t devid, diff --git a/xen/include/asm-arm/gic.h b/xen/include/asm-arm/gic.h index 2f5d5e3..2edf9de 100644 --- a/xen/include/asm-arm/gic.h +++ b/xen/include/asm-arm/gic.h @@ -287,6 +287,8 @@ extern unsigned int gic_number_lines(void); /* LPI support info */ bool_t gic_lpi_supported(void); +void gicv3_host_irq_end(struct irq_desc *desc); +void gicv3_guest_irq_end(struct irq_desc *desc); /* IRQ translation function for the device tree */ int gic_irq_xlate(const u32 *intspec, unsigned int intsize, unsigned int *out_hwirq, unsigned int *out_type); @@ -322,10 +324,10 @@ struct gic_hw_operations { void (*dump_state)(const struct vcpu *); /* hw_irq_controller to enable/disable/eoi host irq */ - hw_irq_controller *gic_host_irq_type; + hw_irq_controller *(*gic_get_host_irq_type)(unsigned int irq); /* hw_irq_controller to enable/disable/eoi guest irq */ - hw_irq_controller *gic_guest_irq_type; + hw_irq_controller *(*gic_get_guest_irq_type)(unsigned int irq); /* End of Interrupt */ void (*eoi_irq)(struct irq_desc *irqd); @@ -364,6 +366,13 @@ struct gic_hw_operations { bool_t (*is_lpi)(unsigned int irq); }; +struct its_hw_operations { + /* hw_irq_controller to enable/disable/eoi host lpi */ + hw_irq_controller *lpi_host_irq_type; + /* hw_irq_controller to enable/disable/eoi guest lpi */ + hw_irq_controller *lpi_guest_irq_type; +}; + void register_gic_ops(const struct gic_hw_operations *ops); int gic_make_hwdom_dt_node(const struct domain *d, const struct dt_device_node *node, diff --git a/xen/include/asm-arm/irq.h b/xen/include/asm-arm/irq.h index f33c331..5923127 100644 --- a/xen/include/asm-arm/irq.h +++ b/xen/include/asm-arm/irq.h @@ -18,6 +18,14 @@ struct arch_irq_desc { unsigned int type; }; +struct msi_desc { +#ifdef HAS_GICV3 + unsigned int eventID; + struct its_device *dev; + u16 col_id; +#endif +}; + #define NR_LOCAL_IRQS 32 #define NR_IRQS 1024 @@ -51,7 +59,12 @@ void arch_move_irqs(struct vcpu *v); /* Set IRQ type for an SPI */ int irq_set_spi_type(unsigned int spi, unsigned int type); - +unsigned int irq_to_virq(struct irq_desc *desc); +unsigned int irq_to_vid(struct irq_desc *desc); +struct its_device *get_irq_its_device(struct irq_desc *desc); +void set_irq_its_device(struct irq_desc *desc, struct its_device *dev); +u16 irqdesc_get_collection(struct irq_desc *desc); +void irqdesc_set_collection(struct irq_desc *desc, u16 col_id); int platform_get_irq(const struct dt_device_node *device, int index); void irq_set_affinity(struct irq_desc *desc, const cpumask_t *cpu_mask); -- 1.7.9.5