[PATCH v3] arm/acpi: Add Server Base System Architecture UART support

[PATCH v3] arm/acpi: Add Server Base System Architecture UART support

[Shanker Donthineni]

The ARM Server Base System Architecture describes a generic UART
interface. It doesn't support clock control registers, modem
control, DMA and hardware flow control features. So, extend the
driver probe() to handle SBSA interface and skip the accessing
PL011 registers that are not described in SBSA document
(ARM-DEN-0029 Version 3.0, 6 APPENDIX B: GENERIC UART).

Signed-off-by: Shanker Donthineni <shankerd@codeaurora.org>
---
Changes since v2:
   Edited commit text to include SBSA document version.
   Remove setting baudrate code completely as per Julien's suggestion.
   Support both the SBSA interface types ACPI_DBG2_SBSA & ACPI_DBG2_SBSA_32.
   Replace MIS references with combination of RIS & IMSC.

Changes since v1:
   Don't access UART registers that are not part of SBSA document.
   Move setting baudrate function to a separate function.

 xen/drivers/char/pl011.c | 76 ++++++++++++++++++++++++++----------------------
 1 file changed, 41 insertions(+), 35 deletions(-)

diff --git a/xen/drivers/char/pl011.c b/xen/drivers/char/pl011.c
index 1212d5c..3497d61 100644
--- a/xen/drivers/char/pl011.c
+++ b/xen/drivers/char/pl011.c
@@ -31,7 +31,7 @@
 #include <asm/io.h>
 
 static struct pl011 {
-    unsigned int baud, clock_hz, data_bits, parity, stop_bits;
+    unsigned int data_bits, parity, stop_bits;
     unsigned int irq;
     void __iomem *regs;
     /* UART with IRQ line: interrupt-driven I/O. */
@@ -41,6 +41,7 @@ static struct pl011 {
     /* struct timer timer; */
     /* unsigned int timeout_ms; */
     /* bool_t probing, intr_works; */
+    bool sbsa;  /* ARM SBSA generic interface */
 } pl011_com = {0};
 
 /* These parity settings can be ORed directly into the LCR. */
@@ -57,7 +58,9 @@ static void pl011_interrupt(int irq, void *data, struct cpu_user_regs *regs)
 {
     struct serial_port *port = data;
     struct pl011 *uart = port->uart;
-    unsigned int status = pl011_read(uart, MIS);
+    unsigned int status = pl011_read(uart, RIS);
+
+    status &= pl011_read(uart, IMSC);
 
     if ( status )
     {
@@ -76,7 +79,7 @@ static void pl011_interrupt(int irq, void *data, struct cpu_user_regs *regs)
             if ( status & (TXI) )
                 serial_tx_interrupt(port, regs);
 
-            status = pl011_read(uart, MIS);
+            status = pl011_read(uart, RIS) & pl011_read(uart, IMSC);
         } while (status != 0);
     }
 }
@@ -84,36 +87,22 @@ static void pl011_interrupt(int irq, void *data, struct cpu_user_regs *regs)
 static void __init pl011_init_preirq(struct serial_port *port)
 {
     struct pl011 *uart = port->uart;
-    unsigned int divisor;
     unsigned int cr;
 
     /* No interrupts, please. */
     pl011_write(uart, IMSC, 0);
 
-    /* Definitely no DMA */
-    pl011_write(uart, DMACR, 0x0);
-
-    /* Line control and baud-rate generator. */
-    if ( uart->baud != BAUD_AUTO )
-    {
-        /* Baud rate specified: program it into the divisor latch. */
-        divisor = (uart->clock_hz << 2) / uart->baud; /* clk << 6 / bd << 4 */
-        pl011_write(uart, FBRD, divisor & 0x3f);
-        pl011_write(uart, IBRD, divisor >> 6);
-    }
-    else
+    if ( !uart->sbsa )
     {
-        /* Baud rate already set: read it out from the divisor latch. */
-        divisor = (pl011_read(uart, IBRD) << 6) | (pl011_read(uart, FBRD));
-        if (!divisor)
-            panic("pl011: No Baud rate configured\n");
-        uart->baud = (uart->clock_hz << 2) / divisor;
+        /* Definitely no DMA */
+        pl011_write(uart, DMACR, 0x0);
+
+        /* This write must follow FBRD and IBRD writes. */
+        pl011_write(uart, LCR_H, (uart->data_bits - 5) << 5
+                                | FEN
+                                | ((uart->stop_bits - 1) << 3)
+                                | uart->parity);
     }
-    /* This write must follow FBRD and IBRD writes. */
-    pl011_write(uart, LCR_H, (uart->data_bits - 5) << 5
-                            | FEN
-                            | ((uart->stop_bits - 1) << 3)
-                            | uart->parity);
     /* Clear errors */
     pl011_write(uart, RSR, 0);
 
@@ -121,10 +110,13 @@ static void __init pl011_init_preirq(struct serial_port *port)
     pl011_write(uart, IMSC, 0);
     pl011_write(uart, ICR, ALLI);
 
-    /* Enable the UART for RX and TX; keep RTS and DTR */
-    cr = pl011_read(uart, CR);
-    cr &= RTS | DTR;
-    pl011_write(uart, CR, cr | RXE | TXE | UARTEN);
+    if ( !uart->sbsa )
+    {
+        /* Enable the UART for RX and TX; keep RTS and DTR */
+        cr = pl011_read(uart, CR);
+        cr &= RTS | DTR;
+        pl011_write(uart, CR, cr | RXE | TXE | UARTEN);
+    }
 }
 
 static void __init pl011_init_postirq(struct serial_port *port)
@@ -226,17 +218,16 @@ static struct uart_driver __read_mostly pl011_driver = {
     .vuart_info   = pl011_vuart,
 };
 
-static int __init pl011_uart_init(int irq, u64 addr, u64 size)
+static int __init pl011_uart_init(int irq, u64 addr, u64 size, bool sbsa)
 {
     struct pl011 *uart;
 
     uart = &pl011_com;
     uart->irq       = irq;
-    uart->clock_hz  = 0x16e3600;
-    uart->baud      = BAUD_AUTO;
     uart->data_bits = 8;
     uart->parity    = PARITY_NONE;
     uart->stop_bits = 1;
+    uart->sbsa = sbsa;
 
     uart->regs = ioremap_nocache(addr, size);
     if ( !uart->regs )
@@ -285,7 +276,7 @@ static int __init pl011_dt_uart_init(struct dt_device_node *dev,
         return -EINVAL;
     }
 
-    res = pl011_uart_init(res, addr, size);
+    res = pl011_uart_init(res, addr, size, false);
     if ( res < 0 )
     {
         printk("pl011: Unable to initialize\n");
@@ -315,6 +306,7 @@ static int __init pl011_acpi_uart_init(const void *data)
 {
     acpi_status status;
     struct acpi_table_spcr *spcr = NULL;
+    bool sbsa = false;
     int res;
 
     status = acpi_get_table(ACPI_SIG_SPCR, 0,
@@ -326,11 +318,15 @@ static int __init pl011_acpi_uart_init(const void *data)
         return -EINVAL;
     }
 
+    if ( (spcr->interface_type == ACPI_DBG2_SBSA) ||
+         (spcr->interface_type == ACPI_DBG2_SBSA_32) )
+        sbsa = true;
+
     /* trigger/polarity information is not available in spcr */
     irq_set_type(spcr->interrupt, IRQ_TYPE_LEVEL_HIGH);
 
     res = pl011_uart_init(spcr->interrupt, spcr->serial_port.address,
-                          PAGE_SIZE);
+                          PAGE_SIZE, sbsa);
     if ( res < 0 )
     {
         printk("pl011: Unable to initialize\n");
@@ -344,6 +340,16 @@ ACPI_DEVICE_START(apl011, "PL011 UART", DEVICE_SERIAL)
         .class_type = ACPI_DBG2_PL011,
         .init = pl011_acpi_uart_init,
 ACPI_DEVICE_END
+
+ACPI_DEVICE_START(asbsa_uart, "SBSA UART", DEVICE_SERIAL)
+        .class_type = ACPI_DBG2_SBSA,
+        .init = pl011_acpi_uart_init,
+ACPI_DEVICE_END
+
+ACPI_DEVICE_START(asbsa32_uart, "SBSA32 UART", DEVICE_SERIAL)
+        .class_type = ACPI_DBG2_SBSA_32,
+        .init = pl011_acpi_uart_init,
+ACPI_DEVICE_END
 #endif
 
 /*
-- 
Qualcomm Technologies, Inc. on behalf of Qualcomm Innovation Center, Inc. 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, 
a Linux Foundation Collaborative Project


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Re: [PATCH v3] arm/acpi: Add Server Base System Architecture UART support

[Julien Grall]

Hi Shanker,

On 03/06/16 18:39, Shanker Donthineni wrote:
> The ARM Server Base System Architecture describes a generic UART
> interface. It doesn't support clock control registers, modem
> control, DMA and hardware flow control features. So, extend the
> driver probe() to handle SBSA interface and skip the accessing
> PL011 registers that are not described in SBSA document
> (ARM-DEN-0029 Version 3.0, 6 APPENDIX B: GENERIC UART).
>
> Signed-off-by: Shanker Donthineni <shankerd@codeaurora.org>
> ---
> Changes since v2:
>     Edited commit text to include SBSA document version.
>     Remove setting baudrate code completely as per Julien's suggestion.

This item and ...

>     Support both the SBSA interface types ACPI_DBG2_SBSA & ACPI_DBG2_SBSA_32.
>     Replace MIS references with combination of RIS & IMSC.

this one need some description in the commit message to explain why it 
is fine for non-SBSA UART to do it.

The later also needs some explanation why MIS could be replaced by RIS & 
IMSC.

Lastly, IHMO those 2 items should be in separate patch to make the 
review easier.

>
> Changes since v1:
>     Don't access UART registers that are not part of SBSA document.
>     Move setting baudrate function to a separate function.
>
>   xen/drivers/char/pl011.c | 76 ++++++++++++++++++++++++++----------------------
>   1 file changed, 41 insertions(+), 35 deletions(-)
>
> diff --git a/xen/drivers/char/pl011.c b/xen/drivers/char/pl011.c
> index 1212d5c..3497d61 100644
> --- a/xen/drivers/char/pl011.c
> +++ b/xen/drivers/char/pl011.c
> @@ -31,7 +31,7 @@
>   #include <asm/io.h>
>
>   static struct pl011 {
> -    unsigned int baud, clock_hz, data_bits, parity, stop_bits;
> +    unsigned int data_bits, parity, stop_bits;
>       unsigned int irq;
>       void __iomem *regs;
>       /* UART with IRQ line: interrupt-driven I/O. */
> @@ -41,6 +41,7 @@ static struct pl011 {
>       /* struct timer timer; */
>       /* unsigned int timeout_ms; */
>       /* bool_t probing, intr_works; */
> +    bool sbsa;  /* ARM SBSA generic interface */
>   } pl011_com = {0};
>
>   /* These parity settings can be ORed directly into the LCR. */
> @@ -57,7 +58,9 @@ static void pl011_interrupt(int irq, void *data, struct cpu_user_regs *regs)
>   {
>       struct serial_port *port = data;
>       struct pl011 *uart = port->uart;
> -    unsigned int status = pl011_read(uart, MIS);
> +    unsigned int status = pl011_read(uart, RIS);
> +
> +    status &= pl011_read(uart, IMSC);
>
>       if ( status )
>       {
> @@ -76,7 +79,7 @@ static void pl011_interrupt(int irq, void *data, struct cpu_user_regs *regs)
>               if ( status & (TXI) )
>                   serial_tx_interrupt(port, regs);
>
> -            status = pl011_read(uart, MIS);
> +            status = pl011_read(uart, RIS) & pl011_read(uart, IMSC);

Please introduce a helper to read the status.

>           } while (status != 0);
>       }
>   }

Regards,

-- 
Julien Grall

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Re: [PATCH v3] arm/acpi: Add Server Base System Architecture UART support

[Shanker Donthineni]

Hi Julien,

On 06/06/2016 11:04 AM, Julien Grall wrote:
> Hi Shanker,
>
> On 03/06/16 18:39, Shanker Donthineni wrote:
>> The ARM Server Base System Architecture describes a generic UART
>> interface. It doesn't support clock control registers, modem
>> control, DMA and hardware flow control features. So, extend the
>> driver probe() to handle SBSA interface and skip the accessing
>> PL011 registers that are not described in SBSA document
>> (ARM-DEN-0029 Version 3.0, 6 APPENDIX B: GENERIC UART).
>>
>> Signed-off-by: Shanker Donthineni <shankerd@codeaurora.org>
>> ---
>> Changes since v2:
>>     Edited commit text to include SBSA document version.
>>     Remove setting baudrate code completely as per Julien's suggestion.
>
> This item and ...
>
>>     Support both the SBSA interface types ACPI_DBG2_SBSA &
> ACPI_DBG2_SBSA_32.
>>     Replace MIS references with combination of RIS & IMSC.
>
> this one need some description in the commit message to explain why it is fine for non-SBSA UART to do it.
>
I have not tested this patch on non-SBSA UART platform, let me apply this change only for SBSA UART driver
for safe side.

> The later also needs some explanation why MIS could be replaced by RIS & IMSC.
>
> Lastly, IHMO those 2 items should be in separate patch to make the review easier.
>
>>
>> Changes since v1:
>>     Don't access UART registers that are not part of SBSA document.
>>     Move setting baudrate function to a separate function.
>>
>>   xen/drivers/char/pl011.c | 76
> ++++++++++++++++++++++++++----------------------
>>   1 file changed, 41 insertions(+), 35 deletions(-)
>>
>> diff --git a/xen/drivers/char/pl011.c b/xen/drivers/char/pl011.c
>> index 1212d5c..3497d61 100644
>> --- a/xen/drivers/char/pl011.c
>> +++ b/xen/drivers/char/pl011.c
>> @@ -31,7 +31,7 @@
>>   #include <asm/io.h>
>>
>>   static struct pl011 {
>> -    unsigned int baud, clock_hz, data_bits, parity, stop_bits;
>> +    unsigned int data_bits, parity, stop_bits;
>>       unsigned int irq;
>>       void __iomem *regs;
>>       /* UART with IRQ line: interrupt-driven I/O. */
>> @@ -41,6 +41,7 @@ static struct pl011 {
>>       /* struct timer timer; */
>>       /* unsigned int timeout_ms; */
>>       /* bool_t probing, intr_works; */
>> +    bool sbsa;  /* ARM SBSA generic interface */
>>   } pl011_com = {0};
>>
>>   /* These parity settings can be ORed directly into the LCR. */
>> @@ -57,7 +58,9 @@ static void pl011_interrupt(int irq, void *data,
> struct cpu_user_regs *regs)
>>   {
>>       struct serial_port *port = data;
>>       struct pl011 *uart = port->uart;
>> -    unsigned int status = pl011_read(uart, MIS);
>> +    unsigned int status = pl011_read(uart, RIS);
>> +
>> +    status &= pl011_read(uart, IMSC);
>>
>>       if ( status )
>>       {
>> @@ -76,7 +79,7 @@ static void pl011_interrupt(int irq, void *data,
> struct cpu_user_regs *regs)
>>               if ( status & (TXI) )
>>                   serial_tx_interrupt(port, regs);
>>
>> -            status = pl011_read(uart, MIS);
>> +            status = pl011_read(uart, RIS) & pl011_read(uart, IMSC);
>
> Please introduce a helper to read the status.
>
>>           } while (status != 0);
>>       }
>>   }
>
> Regards,
>

-- 
Shanker Donthineni
Qualcomm Technologies, Inc. on behalf of Qualcomm Innovation Center, Inc.
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project


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Re: [PATCH v3] arm/acpi: Add Server Base System Architecture UART support

[Julien Grall]

On 06/06/2016 20:55, Shanker Donthineni wrote:
> On 06/06/2016 11:04 AM, Julien Grall wrote:
>> On 03/06/16 18:39, Shanker Donthineni wrote:
>>> The ARM Server Base System Architecture describes a generic UART
>>> interface. It doesn't support clock control registers, modem
>>> control, DMA and hardware flow control features. So, extend the
>>> driver probe() to handle SBSA interface and skip the accessing
>>> PL011 registers that are not described in SBSA document
>>> (ARM-DEN-0029 Version 3.0, 6 APPENDIX B: GENERIC UART).
>>>
>>> Signed-off-by: Shanker Donthineni <shankerd@codeaurora.org>
>>> ---
>>> Changes since v2:
>>>     Edited commit text to include SBSA document version.
>>>     Remove setting baudrate code completely as per Julien's suggestion.
>>
>> This item and ...
>>
>>>     Support both the SBSA interface types ACPI_DBG2_SBSA &
>> ACPI_DBG2_SBSA_32.
>>>     Replace MIS references with combination of RIS & IMSC.
>>
>> this one need some description in the commit message to explain why it is fine for non-SBSA UART to do it.
>>
> I have not tested this patch on non-SBSA UART platform, let me apply this change only for SBSA UART driver
> for safe side.

This patch could be easily tested on the foundation model. I don't want 
to see "if SBSA UART" in the interrupt handler. The code there should be 
straight-forward.

What I am asking for is explaining in a commit message why MIS could be 
replaced by RIS & IMSC. You must have read the doc to find that.

A comment in the code to say this necessary to be SBSA compliant v2.x 
would be good to avoid change reverting back in the future to MIS.

Regards,

-- 
Julien Grall

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