[PATCH V7 1/3] drivers/pl011: Don't configure baudrate

[PATCH V7 1/3] drivers/pl011: Don't configure baudrate

[Shanker Donthineni]

The default baud and clock_hz configuration parameters are hardcoded
(commit 60ff9444480995008caf) for Versatile Express. Other platforms,
these default values may not be valid and might cause problems by
programming registers IBRD and FBRD incorrectly.

So, removing driver logic that sets the baudrate to fix the problem.
The behavior is unchanged because the driver was already relying on
the boot firmware for setting the correct baudrate.

Signed-off-by: Shanker Donthineni <shankerd@codeaurora.org>
Reviewed-by: Julien Grall <julien.grall@arm.com>
---
Changes since v1:
  Edited commit text.

 xen/drivers/char/pl011.c | 21 +--------------------
 1 file changed, 1 insertion(+), 20 deletions(-)

diff --git a/xen/drivers/char/pl011.c b/xen/drivers/char/pl011.c
index 1212d5c..6a3c21b 100644
--- a/xen/drivers/char/pl011.c
+++ b/xen/drivers/char/pl011.c
@@ -31,7 +31,7 @@
 #include <asm/io.h>
 
 static struct pl011 {
-    unsigned int baud, clock_hz, data_bits, parity, stop_bits;
+    unsigned int data_bits, parity, stop_bits;
     unsigned int irq;
     void __iomem *regs;
     /* UART with IRQ line: interrupt-driven I/O. */
@@ -84,7 +84,6 @@ static void pl011_interrupt(int irq, void *data, struct cpu_user_regs *regs)
 static void __init pl011_init_preirq(struct serial_port *port)
 {
     struct pl011 *uart = port->uart;
-    unsigned int divisor;
     unsigned int cr;
 
     /* No interrupts, please. */
@@ -93,22 +92,6 @@ static void __init pl011_init_preirq(struct serial_port *port)
     /* Definitely no DMA */
     pl011_write(uart, DMACR, 0x0);
 
-    /* Line control and baud-rate generator. */
-    if ( uart->baud != BAUD_AUTO )
-    {
-        /* Baud rate specified: program it into the divisor latch. */
-        divisor = (uart->clock_hz << 2) / uart->baud; /* clk << 6 / bd << 4 */
-        pl011_write(uart, FBRD, divisor & 0x3f);
-        pl011_write(uart, IBRD, divisor >> 6);
-    }
-    else
-    {
-        /* Baud rate already set: read it out from the divisor latch. */
-        divisor = (pl011_read(uart, IBRD) << 6) | (pl011_read(uart, FBRD));
-        if (!divisor)
-            panic("pl011: No Baud rate configured\n");
-        uart->baud = (uart->clock_hz << 2) / divisor;
-    }
     /* This write must follow FBRD and IBRD writes. */
     pl011_write(uart, LCR_H, (uart->data_bits - 5) << 5
                             | FEN
@@ -232,8 +215,6 @@ static int __init pl011_uart_init(int irq, u64 addr, u64 size)
 
     uart = &pl011_com;
     uart->irq       = irq;
-    uart->clock_hz  = 0x16e3600;
-    uart->baud      = BAUD_AUTO;
     uart->data_bits = 8;
     uart->parity    = PARITY_NONE;
     uart->stop_bits = 1;
-- 
Qualcomm Technologies, Inc. on behalf of Qualcomm Innovation Center, Inc. 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, 
a Linux Foundation Collaborative Project


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[PATCH V7 2/3] drivers/pl011: Use combination of UARTRIS and UARTMSC instead of UARTMIS

[Shanker Donthineni]

The Masked interrupt status register (UARTMIS) is not described in ARM
SBSA 2.x document. Anding of two registers UARTMSC and UARTRIS values
gives the same information as register UARTMIS.

UARTRIS, UARTMSC and UARTMIS definitions are found in PrimeCell UART
PL011 (Revision: r1p4).
 - 3.3.10 Interrupt mask set/clear register, UARTIMSC
 - 3.3.11 Raw interrupt status register, UARTRIS
 - 3.3.12 Masked interrupt status register, UARTMIS

This change is necessary for driver to be SBSA compliant v2.x without
affecting the current driver functionality.

Signed-off-by: Shanker Donthineni <shankerd@codeaurora.org>
---
Changes since v1:
 Added a new function to return an interrupt status.

 xen/drivers/char/pl011.c | 11 +++++++++--
 1 file changed, 9 insertions(+), 2 deletions(-)

diff --git a/xen/drivers/char/pl011.c b/xen/drivers/char/pl011.c
index 6a3c21b..86fc463 100644
--- a/xen/drivers/char/pl011.c
+++ b/xen/drivers/char/pl011.c
@@ -50,14 +50,21 @@ static struct pl011 {
 #define PARITY_MARK  (PEN|SPS)
 #define PARITY_SPACE (PEN|EPS|SPS)
 
+/* To compatible with SBSA v2.x document, all accesses should be 32-bit */
 #define pl011_read(uart, off)           readl((uart)->regs + (off))
 #define pl011_write(uart, off,val)      writel((val), (uart)->regs + (off))
 
+static unsigned int pl011_intr_status(struct pl011 *uart)
+{
+    /* UARTMIS is not documented in SBSA v2.x, so using UARTRIS/UARTIMSC */
+    return ( pl011_read(uart, RIS) & pl011_read(uart, IMSC) );
+}
+
 static void pl011_interrupt(int irq, void *data, struct cpu_user_regs *regs)
 {
     struct serial_port *port = data;
     struct pl011 *uart = port->uart;
-    unsigned int status = pl011_read(uart, MIS);
+    unsigned int status = pl011_intr_status(uart);
 
     if ( status )
     {
@@ -76,7 +83,7 @@ static void pl011_interrupt(int irq, void *data, struct cpu_user_regs *regs)
             if ( status & (TXI) )
                 serial_tx_interrupt(port, regs);
 
-            status = pl011_read(uart, MIS);
+            status = pl011_intr_status(uart);
         } while (status != 0);
     }
 }
-- 
Qualcomm Technologies, Inc. on behalf of Qualcomm Innovation Center, Inc. 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, 
a Linux Foundation Collaborative Project


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[PATCH V7 3/3] arm/acpi: Add Server Base System Architecture UART support

[Shanker Donthineni]

The ARM Server Base System Architecture describes a generic UART
interface. It doesn't support clock control registers, modem
control, DMA and hardware flow control features. So, extend the
driver probe() to handle SBSA interface and skip the accessing
PL011 registers that are not described in SBSA document
(ARM-DEN-0029 Version 3.0, 6 APPENDIX B: GENERIC UART).

Signed-off-by: Shanker Donthineni <shankerd@codeaurora.org>
Reviewed-by: Julien Grall <julien.grall@arm.com>
---
Changes since v3:
  Moved non-SBSA related changes to patches 1/3 and 2/3.

changes since v2:
  Edited commit text to include SBSA document version.
  Remove setting baudrate code completely as per Julien's suggestion.
  Support both the SBSA interface types ACPI_DBG2_SBSA & ACPI_DBG2_SBSA_32.
  Replace MIS references with combination of RIS & IMSC.

Changes since v1:
  Don't access UART registers that are not part of SBSA document.
  Move setting baudrate function to a separate function.

 xen/drivers/char/pl011.c | 54 ++++++++++++++++++++++++++++++++++--------------
 1 file changed, 39 insertions(+), 15 deletions(-)

diff --git a/xen/drivers/char/pl011.c b/xen/drivers/char/pl011.c
index 86fc463..d70ec99 100644
--- a/xen/drivers/char/pl011.c
+++ b/xen/drivers/char/pl011.c
@@ -41,6 +41,7 @@ static struct pl011 {
     /* struct timer timer; */
     /* unsigned int timeout_ms; */
     /* bool_t probing, intr_works; */
+    bool sbsa;  /* ARM SBSA generic interface */
 } pl011_com = {0};
 
 /* These parity settings can be ORed directly into the LCR. */
@@ -96,14 +97,17 @@ static void __init pl011_init_preirq(struct serial_port *port)
     /* No interrupts, please. */
     pl011_write(uart, IMSC, 0);
 
-    /* Definitely no DMA */
-    pl011_write(uart, DMACR, 0x0);
-
-    /* This write must follow FBRD and IBRD writes. */
-    pl011_write(uart, LCR_H, (uart->data_bits - 5) << 5
-                            | FEN
-                            | ((uart->stop_bits - 1) << 3)
-                            | uart->parity);
+    if ( !uart->sbsa )
+    {
+        /* Definitely no DMA */
+        pl011_write(uart, DMACR, 0x0);
+
+        /* This write must follow FBRD and IBRD writes. */
+        pl011_write(uart, LCR_H, (uart->data_bits - 5) << 5
+                                | FEN
+                                | ((uart->stop_bits - 1) << 3)
+                                | uart->parity);
+    }
     /* Clear errors */
     pl011_write(uart, RSR, 0);
 
@@ -111,10 +115,13 @@ static void __init pl011_init_preirq(struct serial_port *port)
     pl011_write(uart, IMSC, 0);
     pl011_write(uart, ICR, ALLI);
 
-    /* Enable the UART for RX and TX; keep RTS and DTR */
-    cr = pl011_read(uart, CR);
-    cr &= RTS | DTR;
-    pl011_write(uart, CR, cr | RXE | TXE | UARTEN);
+    if ( !uart->sbsa )
+    {
+        /* Enable the UART for RX and TX; keep RTS and DTR */
+        cr = pl011_read(uart, CR);
+        cr &= RTS | DTR;
+        pl011_write(uart, CR, cr | RXE | TXE | UARTEN);
+    }
 }
 
 static void __init pl011_init_postirq(struct serial_port *port)
@@ -216,7 +223,7 @@ static struct uart_driver __read_mostly pl011_driver = {
     .vuart_info   = pl011_vuart,
 };
 
-static int __init pl011_uart_init(int irq, u64 addr, u64 size)
+static int __init pl011_uart_init(int irq, u64 addr, u64 size, bool sbsa)
 {
     struct pl011 *uart;
 
@@ -225,6 +232,7 @@ static int __init pl011_uart_init(int irq, u64 addr, u64 size)
     uart->data_bits = 8;
     uart->parity    = PARITY_NONE;
     uart->stop_bits = 1;
+    uart->sbsa      = sbsa;
 
     uart->regs = ioremap_nocache(addr, size);
     if ( !uart->regs )
@@ -273,7 +281,7 @@ static int __init pl011_dt_uart_init(struct dt_device_node *dev,
         return -EINVAL;
     }
 
-    res = pl011_uart_init(res, addr, size);
+    res = pl011_uart_init(res, addr, size, false);
     if ( res < 0 )
     {
         printk("pl011: Unable to initialize\n");
@@ -304,6 +312,7 @@ static int __init pl011_acpi_uart_init(const void *data)
     acpi_status status;
     struct acpi_table_spcr *spcr = NULL;
     int res;
+    bool sbsa = false;
 
     status = acpi_get_table(ACPI_SIG_SPCR, 0,
                             (struct acpi_table_header **)&spcr);
@@ -314,11 +323,15 @@ static int __init pl011_acpi_uart_init(const void *data)
         return -EINVAL;
     }
 
+    if ( (spcr->interface_type == ACPI_DBG2_SBSA) ||
+         (spcr->interface_type == ACPI_DBG2_SBSA_32) )
+        sbsa = true;
+
     /* trigger/polarity information is not available in spcr */
     irq_set_type(spcr->interrupt, IRQ_TYPE_LEVEL_HIGH);
 
     res = pl011_uart_init(spcr->interrupt, spcr->serial_port.address,
-                          PAGE_SIZE);
+                          PAGE_SIZE, sbsa);
     if ( res < 0 )
     {
         printk("pl011: Unable to initialize\n");
@@ -332,6 +345,17 @@ ACPI_DEVICE_START(apl011, "PL011 UART", DEVICE_SERIAL)
         .class_type = ACPI_DBG2_PL011,
         .init = pl011_acpi_uart_init,
 ACPI_DEVICE_END
+
+ACPI_DEVICE_START(asbsa_uart, "SBSA UART", DEVICE_SERIAL)
+    .class_type = ACPI_DBG2_SBSA,
+    .init = pl011_acpi_uart_init,
+ACPI_DEVICE_END
+
+ACPI_DEVICE_START(asbsa32_uart, "SBSA32 UART", DEVICE_SERIAL)
+    .class_type = ACPI_DBG2_SBSA_32,
+    .init = pl011_acpi_uart_init,
+ACPI_DEVICE_END
+
 #endif
 
 /*
-- 
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Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, 
a Linux Foundation Collaborative Project


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Re: [PATCH V7 2/3] drivers/pl011: Use combination of UARTRIS and UARTMSC instead of UARTMIS

[Julien Grall]

Hi Shanker,

On 07/06/2016 20:04, Shanker Donthineni wrote:
> The Masked interrupt status register (UARTMIS) is not described in ARM
> SBSA 2.x document. Anding of two registers UARTMSC and UARTRIS values
> gives the same information as register UARTMIS.
>
> UARTRIS, UARTMSC and UARTMIS definitions are found in PrimeCell UART
> PL011 (Revision: r1p4).
>  - 3.3.10 Interrupt mask set/clear register, UARTIMSC
>  - 3.3.11 Raw interrupt status register, UARTRIS
>  - 3.3.12 Masked interrupt status register, UARTMIS
>
> This change is necessary for driver to be SBSA compliant v2.x without
> affecting the current driver functionality.
>
> Signed-off-by: Shanker Donthineni <shankerd@codeaurora.org>
> ---
> Changes since v1:
>  Added a new function to return an interrupt status.
>
>  xen/drivers/char/pl011.c | 11 +++++++++--
>  1 file changed, 9 insertions(+), 2 deletions(-)
>
> diff --git a/xen/drivers/char/pl011.c b/xen/drivers/char/pl011.c
> index 6a3c21b..86fc463 100644
> --- a/xen/drivers/char/pl011.c
> +++ b/xen/drivers/char/pl011.c
> @@ -50,14 +50,21 @@ static struct pl011 {
>  #define PARITY_MARK  (PEN|SPS)
>  #define PARITY_SPACE (PEN|EPS|SPS)
>
> +/* To compatible with SBSA v2.x document, all accesses should be 32-bit */

This comment does not belong to this patch but the next one (#3).

Regards,

-- 
Julien Grall

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