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From: Shanker Donthineni <shankerd@codeaurora.org>
To: xen-devel <xen-devel@lists.xensource.com>,
	Julien Grall <julien.grall@arm.com>,
	Stefano Stabellini <sstabellini@kernel.org>
Cc: Andre Przywara <andre.przywara@arm.com>,
	Philip Elcan <pelcan@codeaurora.org>,
	Shanker Donthineni <shankerd@codeaurora.org>,
	Vikram Sethi <vikrams@codeaurora.org>,
	Wei Chen <wei.chen@linaro.org>
Subject: [PATCH V9 2/3] drivers/pl011: Use combination of UARTRIS and UARTMSC instead of UARTMIS
Date: Thu,  9 Jun 2016 12:33:20 -0500	[thread overview]
Message-ID: <1465493601-15182-2-git-send-email-shankerd@codeaurora.org> (raw)
In-Reply-To: <1465493601-15182-1-git-send-email-shankerd@codeaurora.org>

The Masked interrupt status register (UARTMIS) is not described in ARM
SBSA 2.x document. Anding of two registers UARTMSC and UARTRIS values
gives the same information as register UARTMIS.

UARTRIS, UARTMSC and UARTMIS definitions are found in PrimeCell UART
PL011 (Revision: r1p4).
 - 3.3.10 Interrupt mask set/clear register, UARTIMSC
 - 3.3.11 Raw interrupt status register, UARTRIS
 - 3.3.12 Masked interrupt status register, UARTMIS

This change is necessary for driver to be SBSA compliant v2.x without
affecting the current driver functionality.

Signed-off-by: Shanker Donthineni <shankerd@codeaurora.org>
Reviewed-by: Julien Grall <julien.grall@arm.com>
---
Changes since v8:
 Fixed white spaces.

Changes since v7:
 Moved comment 'To compatible with SBSA v2.x document, all accesses should be 32-bit' to #3

Changes since v1:
 Added a new function to return an interrupt status.

 xen/drivers/char/pl011.c | 10 ++++++++--
 1 file changed, 8 insertions(+), 2 deletions(-)

diff --git a/xen/drivers/char/pl011.c b/xen/drivers/char/pl011.c
index 6a3c21b..7e19c4a 100644
--- a/xen/drivers/char/pl011.c
+++ b/xen/drivers/char/pl011.c
@@ -53,11 +53,17 @@ static struct pl011 {
 #define pl011_read(uart, off)           readl((uart)->regs + (off))
 #define pl011_write(uart, off,val)      writel((val), (uart)->regs + (off))
 
+static unsigned int pl011_intr_status(struct pl011 *uart)
+{
+    /* UARTMIS is not documented in SBSA v2.x, so use UARTRIS/UARTIMSC. */
+    return (pl011_read(uart, RIS) & pl011_read(uart, IMSC));
+}
+
 static void pl011_interrupt(int irq, void *data, struct cpu_user_regs *regs)
 {
     struct serial_port *port = data;
     struct pl011 *uart = port->uart;
-    unsigned int status = pl011_read(uart, MIS);
+    unsigned int status = pl011_intr_status(uart);
 
     if ( status )
     {
@@ -76,7 +82,7 @@ static void pl011_interrupt(int irq, void *data, struct cpu_user_regs *regs)
             if ( status & (TXI) )
                 serial_tx_interrupt(port, regs);
 
-            status = pl011_read(uart, MIS);
+            status = pl011_intr_status(uart);
         } while (status != 0);
     }
 }
-- 
Qualcomm Technologies, Inc. on behalf of Qualcomm Innovation Center, Inc. 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, 
a Linux Foundation Collaborative Project


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  reply	other threads:[~2016-06-09 17:33 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-06-09 17:33 [PATCH V9 1/3] drivers/pl011: Don't configure baudrate Shanker Donthineni
2016-06-09 17:33 ` Shanker Donthineni [this message]
2016-06-13 10:30   ` [PATCH V9 2/3] drivers/pl011: Use combination of UARTRIS and UARTMSC instead of UARTMIS Stefano Stabellini
2016-06-13 17:43     ` Shanker Donthineni
2016-06-14 14:53       ` Julien Grall
2016-06-09 17:33 ` [PATCH V9 3/3] arm/acpi: Add Server Base System Architecture UART support Shanker Donthineni

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