[PATCH] xen/arm64: Use the correct TLBs flush instruction to nuke stage-2 TLBs

[PATCH] xen/arm64: Use the correct TLBs flush instruction to nuke stage-2 TLBs

[Julien Grall]

The function flush_tlb is called to invalidate the TLBs for the current
domain when the stage-2 page tables are modified.

On ARMv8, the instruction "tlbi vmalle1is" (resp. "tlbi vmalle1") will
invalidate stage 1 entries associated to the current VMID (see D4-1811 in
ARM DDI 0487A.j).

Given that an implementation is allowed to cache separately stage 1 and
stage 2 translation (see D4.7.1), the instructions will not remove stage
2 entries when the translation is not combined in a single entry.
This will result the TLBs to hold invalid entries and possibly multiple
entries using the same VA.

Use "tlbi vmall12e1is" (resp. "tlbi vmall12e1"), to flush both stage 1
and stage 2 entries when the domain p2m is changed.

Also modify flush_tlb_local to invalidate stage 1 and 2 for the local
TLBs. Note that this function is used in the instruction abort path
before translating a GVA to a IPA. As far as I understand is to avoid a
guest poisoning the DTLB when memacces is in use. We might be able to
only invalidate stage 1 entries. However, I choose the safest way for now
(i.e invalidating stage 1 and 2 entries). We would need to introduce a
new set of helpers when we will want to restrict it.

Signed-off-by: Julien Grall <julien.grall@arm.com>

--
    This would need to be backported on any version of Xen currently
    supported (IIRC think up to Xen 4.5).

    Without this patch, stage 2 TLBs won't be flushed if the TLBs
    cache intermediate translations entries (IPA -> PA).
---
 xen/include/asm-arm/arm64/flushtlb.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/xen/include/asm-arm/arm64/flushtlb.h b/xen/include/asm-arm/arm64/flushtlb.h
index a73df92..942f2d3 100644
--- a/xen/include/asm-arm/arm64/flushtlb.h
+++ b/xen/include/asm-arm/arm64/flushtlb.h
@@ -6,7 +6,7 @@ static inline void flush_tlb_local(void)
 {
     asm volatile(
         "dsb sy;"
-        "tlbi vmalle1;"
+        "tlbi vmalls12e1;"
         "dsb sy;"
         "isb;"
         : : : "memory");
@@ -17,7 +17,7 @@ static inline void flush_tlb(void)
 {
     asm volatile(
         "dsb sy;"
-        "tlbi vmalle1is;"
+        "tlbi vmalls12e1is;"
         "dsb sy;"
         "isb;"
         : : : "memory");
-- 
1.9.1


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Re: [PATCH] xen/arm64: Use the correct TLBs flush instruction to nuke stage-2 TLBs

[Stefano Stabellini]

On Thu, 7 Jul 2016, Julien Grall wrote:
> The function flush_tlb is called to invalidate the TLBs for the current
> domain when the stage-2 page tables are modified.
> 
> On ARMv8, the instruction "tlbi vmalle1is" (resp. "tlbi vmalle1") will
> invalidate stage 1 entries associated to the current VMID (see D4-1811 in
> ARM DDI 0487A.j).
> 
> Given that an implementation is allowed to cache separately stage 1 and
> stage 2 translation (see D4.7.1), the instructions will not remove stage
> 2 entries when the translation is not combined in a single entry.
> This will result the TLBs to hold invalid entries and possibly multiple
> entries using the same VA.
> 
> Use "tlbi vmall12e1is" (resp. "tlbi vmall12e1"), to flush both stage 1
                ^ vmalls12e1is          ^ vmalls12e1

Please fix the commit message using the right commands.


> and stage 2 entries when the domain p2m is changed.
> 
> Also modify flush_tlb_local to invalidate stage 1 and 2 for the local
> TLBs. Note that this function is used in the instruction abort path
> before translating a GVA to a IPA. As far as I understand is to avoid a
> guest poisoning the DTLB when memacces is in use. We might be able to
> only invalidate stage 1 entries. However, I choose the safest way for now
> (i.e invalidating stage 1 and 2 entries). We would need to introduce a
> new set of helpers when we will want to restrict it.
> 
> Signed-off-by: Julien Grall <julien.grall@arm.com>
> 
> --
>     This would need to be backported on any version of Xen currently
>     supported (IIRC think up to Xen 4.5).
> 
>     Without this patch, stage 2 TLBs won't be flushed if the TLBs
>     cache intermediate translations entries (IPA -> PA).
> ---
>  xen/include/asm-arm/arm64/flushtlb.h | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/xen/include/asm-arm/arm64/flushtlb.h b/xen/include/asm-arm/arm64/flushtlb.h
> index a73df92..942f2d3 100644
> --- a/xen/include/asm-arm/arm64/flushtlb.h
> +++ b/xen/include/asm-arm/arm64/flushtlb.h
> @@ -6,7 +6,7 @@ static inline void flush_tlb_local(void)
>  {
>      asm volatile(
>          "dsb sy;"
> -        "tlbi vmalle1;"
> +        "tlbi vmalls12e1;"
>          "dsb sy;"
>          "isb;"
>          : : : "memory");
> @@ -17,7 +17,7 @@ static inline void flush_tlb(void)
>  {
>      asm volatile(
>          "dsb sy;"
> -        "tlbi vmalle1is;"
> +        "tlbi vmalls12e1is;"
>          "dsb sy;"
>          "isb;"
>          : : : "memory");
> -- 
> 1.9.1
> 

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