From mboxrd@z Thu Jan 1 00:00:00 1970 From: Dario Faggioli Subject: Re: [PATCH 2/3] xen: Have schedulers revise initial placement Date: Mon, 18 Jul 2016 20:55:06 +0200 Message-ID: <1468868106.13039.170.camel@citrix.com> References: <1468605722-24239-1-git-send-email-george.dunlap@citrix.com> <1468605722-24239-2-git-send-email-george.dunlap@citrix.com> <1468678323.13039.132.camel@citrix.com> <6bfba010-3712-8d43-f866-38b3bfc1444f@citrix.com> Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="===============9022527331425884404==" Return-path: Received: from mail6.bemta3.messagelabs.com ([195.245.230.39]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1bPDhC-0006p6-DV for xen-devel@lists.xenproject.org; Mon, 18 Jul 2016 18:55:14 +0000 In-Reply-To: <6bfba010-3712-8d43-f866-38b3bfc1444f@citrix.com> List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" To: Andrew Cooper , George Dunlap , xen-devel@lists.xenproject.org Cc: Anshul Makkar , Meng Xu , Jan Beulich List-Id: xen-devel@lists.xenproject.org --===============9022527331425884404== Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="=-b0WgflyGr2MOuw98Hvh8" --=-b0WgflyGr2MOuw98Hvh8 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Mon, 2016-07-18 at 19:10 +0100, Andrew Cooper wrote: > On 16/07/16 15:12, Dario Faggioli wrote: > > On Fri, 2016-07-15 at 19:07 +0100, Andrew Cooper wrote: > > So you have to always keep IRQ enabled, for all scheduling > > operations, > > which is ok for _almost_ all of them, with the only exception of > > the > > wakeup of a vcpu. > I know that it is all or nothing.=C2=A0=C2=A0What specific action about w= aking > a > vcpu requires holding a lock? >=20 > If it is simply re-queueing the vcpu onto the runable queue, there > are a > number of lockless queuing algorithms which can be used. >=20 Yes, it's vcpu_wake() that does vcpu_schedule_lock_irqsave() before, among other things, calling SCHED_OP(wake, v). What the implementation of that hook does, is scheduler dependant. In most of the case, the core of it is, as you say, enqueueing the vcpu, but that may not be all. For instance, something that, all the schedulers, after queueing, do is tickling pCPUs for having them pick up the queued work, and that also requires serialization to be correct and effective (i.e., "just" turning and mandating runqueues to be lockless would not be enough). > ~Andrew --=20 <> (Raistlin Majere) ----------------------------------------------------------------- Dario Faggioli, Ph.D, http://about.me/dario.faggioli Senior Software Engineer, Citrix Systems R&D Ltd., Cambridge (UK) --=-b0WgflyGr2MOuw98Hvh8 Content-Type: application/pgp-signature; name="signature.asc" Content-Description: This is a digitally signed message part Content-Transfer-Encoding: 7bit -----BEGIN PGP SIGNATURE----- Version: GnuPG v2 iQIcBAABCAAGBQJXjSYLAAoJEBZCeImluHPuwREP/ie1SWoYbZoxAzHyelDTZ4fP c1yHRKvRi05eqPXQuDv2ksSxaqySZ5WlRlJgMWBllhc+9LdBWhIsYyrL/d6wolWo /rNkbwZa+e926UfEV33b/tuSByQqdYY+adQlsgabBR4YwZRc/OZR+hwE11MVcScv /7ihR0VZG2/YjKfsuoMUyZgY99zlW9GXiHzHo7ObHK8Dych03U6V1vXhUL4jjSmu 7K4bnCMXJX/R3Kf+jV+MhHmQqaK/pUzL7cZFg1EPf+50FjOcozeoRdE+R6fld5Cj zu8lfltujLADicYJC6Dl0Ssb5jwWfTVs0JmizvFYlB7qxs1uGrphT3j/1zMIYdZI ybQIdbdfRg+0VbS3b7+XAnakXis1zbe9jHMOFPidm2Db8fk7OjMxHKzD6YUI7JhX osx1ekhp7fY8BYJvMypUll9lcqJNtTXnErKBa2e8Uahcw2Hj2DdlsaFLeRgkb43e iaYR/nTVQMiFShmLBZs/4/qeCPgCMZJsHQJjvn8O0a5inAkXaE+i24YWPxLTrgXi Ex+cbpTyN/IGkuTMgb4lbyF5/rC5InV5Wgo0Ut/wUS6EXpHrg3PO4VnMJybXftT9 CWN4WUeHcITiWLVHU913XuGRb5ihKnYgiqWHo8lQmyNPzDxuKuOSxNeKxYflJY9N sMYk+R9yiSv3HBcGyJSi =aGPc -----END PGP SIGNATURE----- --=-b0WgflyGr2MOuw98Hvh8-- --===============9022527331425884404== Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: base64 Content-Disposition: inline X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX18KWGVuLWRldmVs IG1haWxpbmcgbGlzdApYZW4tZGV2ZWxAbGlzdHMueGVuLm9yZwpodHRwczovL2xpc3RzLnhlbi5v cmcveGVuLWRldmVsCg== --===============9022527331425884404==--