From: Jan Beulich <jbeulich@suse.com>
To: Andrew Cooper <andrew.cooper3@citrix.com>
Cc: "xen-devel@lists.xenproject.org" <xen-devel@lists.xenproject.org>,
Paul Durrant <Paul.Durrant@citrix.com>, Wei Liu <wl@xen.org>,
Roger Pau Monne <roger.pau@citrix.com>
Subject: Re: [Xen-devel] [PATCH v5 02/10] x86emul: support MOVDIRI insn
Date: Thu, 26 Mar 2020 10:20:39 +0100 [thread overview]
Message-ID: <1bd9dd9e-7603-8332-6ad0-395e48e2cfe2@suse.com> (raw)
In-Reply-To: <f3ccdba4-736e-4e30-028f-2b571724cdf6@citrix.com>
On 25.03.2020 21:58, Andrew Cooper wrote:
> On 24/03/2020 12:29, Jan Beulich wrote:
>> Note that SDM revision 070 doesn't specify exception behavior for
>> ModRM.mod == 0b11; assuming #UD here.
>
> Didn't I confirm this behaviour for you last time around?
Iirc you did, but the SDM still hasn't changed. Do you have a
suggestion on alternative wording.
>> @@ -10075,6 +10079,14 @@ x86_emulate(
>> : "0" ((uint32_t)src.val), "rm" (_regs.edx) );
>> break;
>>
>> + case X86EMUL_OPC(0x0f38, 0xf9): /* movdiri mem,r */
>> + vcpu_must_have(movdiri);
>> + generate_exception_if(dst.type != OP_MEM, EXC_UD);
>> + /* Ignore the non-temporal behavior for now. */
>> + dst.val = src.val;
>> + sfence = true;
>
> Looking again at the SDM, I'm not entirely sure this is good enough.
>
> Even on top of WB/WP mappings, it needs to have WC properties, knock
> aliasing lines out of the cache, and ending up as a bus transaction.
>
> Also, I'm not convinced the current chunking algorithm for qemu which
> repeatedly subdivides down to 1, is compatible with the misaligned
> behaviour described, guaranteeing a split of two.
Taking care of these two will be a significant amount of (re-)work of
the HVM emulation layer. I'll see if I can come up with time and ideas
on how to do this.
Jan
next prev parent reply other threads:[~2020-03-26 9:20 UTC|newest]
Thread overview: 39+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-03-24 12:26 [Xen-devel] [PATCH v5 00/10] x86emul: further work Jan Beulich
2020-03-24 12:29 ` [Xen-devel] [PATCH v5 02/10] x86emul: support AVX512_BF16 insns Jan Beulich
2020-03-24 12:29 ` [Xen-devel] [PATCH v5 02/10] x86emul: support MOVDIRI insn Jan Beulich
2020-03-25 20:58 ` Andrew Cooper
2020-03-26 9:20 ` Jan Beulich [this message]
2020-03-24 12:30 ` [Xen-devel] [PATCH v5 01/10] x86emul: support AVX512_BF16 insns Jan Beulich
2020-03-25 20:02 ` Andrew Cooper
2020-03-27 18:20 ` Andrew Cooper
2020-03-30 6:40 ` Jan Beulich
2020-03-24 12:33 ` [Xen-devel] [PATCH v5 03/10] x86: determine HAVE_AS_* just once Jan Beulich
2020-03-25 21:12 ` Andrew Cooper
2020-03-26 9:50 ` Jan Beulich
2020-03-26 13:42 ` Anthony PERARD
2020-03-26 14:20 ` Jan Beulich
2020-04-09 12:24 ` Jan Beulich
2020-03-24 12:33 ` [Xen-devel] [PATCH v5 04/10] x86: move back clang no integrated assembler tests Jan Beulich
2020-03-24 12:34 ` [Xen-devel] [PATCH v5 05/10] x86emul: support MOVDIR64B insn Jan Beulich
2020-03-25 11:19 ` Paul Durrant
2020-03-25 11:46 ` Jan Beulich
2020-04-02 23:12 ` Andrew Cooper
2020-04-03 7:57 ` Jan Beulich
2020-04-03 15:13 ` Andrew Cooper
2020-04-03 15:25 ` Jan Beulich
2020-03-24 12:34 ` [Xen-devel] [PATCH v5 06/10] x86emul: support ENQCMD insn Jan Beulich
2020-03-24 12:35 ` [Xen-devel] [PATCH v5 07/10] x86/HVM: scale MPERF values reported to guests (on AMD) Jan Beulich
2020-03-24 12:36 ` [Xen-devel] [PATCH v5 08/10] x86emul: support RDPRU Jan Beulich
2020-03-24 12:37 ` [Xen-devel] [PATCH v5 09/10] x86/HVM: don't needlessly intercept APERF/MPERF/TSC MSR reads Jan Beulich
2020-03-27 2:24 ` Tian, Kevin
2020-03-24 12:37 ` [Xen-devel] [PATCH v5 10/10] x86emul: support MCOMMIT Jan Beulich
2020-04-02 23:47 ` Andrew Cooper
2020-04-03 8:00 ` Jan Beulich
2020-04-03 15:00 ` Andrew Cooper
2020-04-03 15:09 ` Jan Beulich
2020-04-03 15:25 ` Andrew Cooper
2020-03-24 12:43 ` [Xen-devel] [PATCH v5 00/10] x86emul: further work Jan Beulich
2020-03-25 10:59 ` Paul Durrant
2020-03-25 11:41 ` Andrew Cooper
2020-03-25 11:45 ` Jan Beulich
2020-03-26 11:49 ` Jan Beulich
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