From: Wei Liu <wei.liu2@citrix.com>
To: Jan Beulich <JBeulich@suse.com>
Cc: Stefano Stabellini <sstabellini@kernel.org>,
Wei Liu <wei.liu2@citrix.com>,
George Dunlap <George.Dunlap@eu.citrix.com>,
Andrew Cooper <andrew.cooper3@citrix.com>,
Ian Jackson <Ian.Jackson@eu.citrix.com>, Tim Deegan <tim@xen.org>,
xen-devel <xen-devel@lists.xenproject.org>,
Feng Wu <feng.wu@intel.com>
Subject: Re: Ping: [PATCH v3 2/4] x86: suppress SMEP and SMAP while running 32-bit PV guest code
Date: Fri, 13 May 2016 16:21:29 +0100 [thread overview]
Message-ID: <20160513152129.GD8974@citrix.com> (raw)
In-Reply-To: <5728CAC202000078000E80D8@prv-mh.provo.novell.com>
On Tue, May 03, 2016 at 07:58:58AM -0600, Jan Beulich wrote:
> >>> On 17.03.16 at 09:03, wrote:
> > Since such guests' kernel code runs in ring 1, their memory accesses,
> > at the paging layer, are supervisor mode ones, and hence subject to
> > SMAP/SMEP checks. Such guests cannot be expected to be aware of those
> > two features though (and so far we also don't expose the respective
> > feature flags), and hence may suffer page faults they cannot deal with.
> >
> > While the placement of the re-enabling slightly weakens the intended
> > protection, it was selected such that 64-bit paths would remain
> > unaffected where possible. At the expense of a further performance hit
> > the re-enabling could be put right next to the CLACs.
> >
> > Note that this introduces a number of extra TLB flushes - CR4.SMEP
> > transitioning from 0 to 1 always causes a flush, and it transitioning
> > from 1 to 0 may also do.
> >
> > Signed-off-by: Jan Beulich <jbeulich@suse.com>
>
> So I think we need to take some decision here, and I'm afraid
> Andrew and I won't be able to settle this between us. He's
> validly concerned about the performance impact this got proven
> to have (for 32-bit PV guests), yet I continue to think that correct
> behavior is more relevant than performance. Hence I think we
> should bite the bullet and take the change. For those who value
> performance more than security, they can always disable the use
> of SMEP and SMAP via command line option.
>
> Of course I'm also concerned that Intel, who did introduce the
> functional regression in the first place, so far didn't participate at
> all in finding an acceptable solution to the problem at hand...
>
So this thread has not produced a conclusion. What do we need to do
about this issue?
Do we have a set of patches that make things behave correctly
(regardless of its performance impact)?
Wei.
> Jan
>
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next prev parent reply other threads:[~2016-05-13 15:21 UTC|newest]
Thread overview: 67+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-03-04 11:08 [PATCH 0/4] x86: accommodate 32-bit PV guests with SMAP/SMEP handling Jan Beulich
2016-03-04 11:27 ` [PATCH 1/4] x86/alternatives: correct near branch check Jan Beulich
2016-03-07 15:43 ` Andrew Cooper
2016-03-07 15:56 ` Jan Beulich
2016-03-07 16:11 ` Andrew Cooper
2016-03-07 16:21 ` Jan Beulich
2016-03-08 17:33 ` Andrew Cooper
2016-03-04 11:27 ` [PATCH 2/4] x86: suppress SMAP and SMEP while running 32-bit PV guest code Jan Beulich
2016-03-07 16:59 ` Andrew Cooper
2016-03-08 7:57 ` Jan Beulich
2016-03-09 8:09 ` Wu, Feng
2016-03-09 14:09 ` Jan Beulich
2016-03-09 11:19 ` Andrew Cooper
2016-03-09 14:28 ` Jan Beulich
2016-03-09 8:09 ` Wu, Feng
2016-03-09 10:45 ` Andrew Cooper
2016-03-09 12:27 ` Wu, Feng
2016-03-09 12:33 ` Andrew Cooper
2016-03-09 12:36 ` Jan Beulich
2016-03-09 12:54 ` Wu, Feng
2016-03-09 13:35 ` Wu, Feng
2016-03-09 13:42 ` Andrew Cooper
2016-03-09 14:03 ` Jan Beulich
2016-03-09 14:07 ` Jan Beulich
2016-03-04 11:28 ` [PATCH 3/4] x86: use optimal NOPs to fill the SMAP/SMEP placeholders Jan Beulich
2016-03-07 17:43 ` Andrew Cooper
2016-03-08 8:02 ` Jan Beulich
2016-03-04 11:29 ` [PATCH 4/4] x86: use 32-bit loads for 32-bit PV guest state reload Jan Beulich
2016-03-07 17:45 ` Andrew Cooper
2016-03-10 9:44 ` [PATCH v2 0/3] x86: accommodate 32-bit PV guests with SMEP/SMAP handling Jan Beulich
2016-03-10 9:53 ` [PATCH v2 1/3] x86: suppress SMEP and SMAP while running 32-bit PV guest code Jan Beulich
2016-05-13 15:48 ` Andrew Cooper
2016-03-10 9:54 ` [PATCH v2 2/3] x86: use optimal NOPs to fill the SMEP/SMAP placeholders Jan Beulich
2016-05-13 15:49 ` Andrew Cooper
2016-03-10 9:55 ` [PATCH v2 3/3] x86: use 32-bit loads for 32-bit PV guest state reload Jan Beulich
[not found] ` <56E9A0DB02000078000DD54C@prv-mh.provo.novell.com>
2016-03-17 7:50 ` [PATCH v3 0/4] x86: accommodate 32-bit PV guests with SMEP/SMAP handling Jan Beulich
2016-03-17 8:02 ` [PATCH v3 1/4] x86: move cached CR4 value to struct cpu_info Jan Beulich
2016-03-17 16:20 ` Andrew Cooper
2016-03-17 8:03 ` [PATCH v3 2/4] x86: suppress SMEP and SMAP while running 32-bit PV guest code Jan Beulich
2016-03-25 18:01 ` Konrad Rzeszutek Wilk
2016-03-29 6:55 ` Jan Beulich
2016-05-13 15:58 ` Andrew Cooper
2016-03-17 8:03 ` [PATCH v3 3/4] x86: use optimal NOPs to fill the SMEP/SMAP placeholders Jan Beulich
2016-05-13 15:57 ` Andrew Cooper
2016-05-13 16:06 ` Jan Beulich
2016-05-13 16:09 ` Andrew Cooper
2016-03-17 8:04 ` [PATCH v3 4/4] x86: use 32-bit loads for 32-bit PV guest state reload Jan Beulich
2016-03-25 18:02 ` Konrad Rzeszutek Wilk
2016-03-17 16:14 ` [PATCH v3 5/4] x86: reduce code size of struct cpu_info member accesses Jan Beulich
2016-03-25 18:47 ` Konrad Rzeszutek Wilk
2016-03-29 6:59 ` Jan Beulich
2016-03-30 14:28 ` Konrad Rzeszutek Wilk
2016-03-30 14:42 ` Jan Beulich
2016-05-13 16:11 ` Andrew Cooper
2016-05-03 13:58 ` Ping: [PATCH v3 2/4] x86: suppress SMEP and SMAP while running 32-bit PV guest code Jan Beulich
2016-05-03 14:10 ` Andrew Cooper
2016-05-03 14:25 ` Jan Beulich
2016-05-04 10:03 ` Andrew Cooper
2016-05-04 13:35 ` Jan Beulich
2016-05-04 3:07 ` Wu, Feng
2016-05-13 15:21 ` Wei Liu [this message]
2016-05-13 15:30 ` Jan Beulich
2016-05-13 15:33 ` Wei Liu
2016-05-13 17:02 ` [PATCH v3 0/4] x86: accommodate 32-bit PV guests with SMEP/SMAP handling Wei Liu
2016-05-13 17:21 ` Andrew Cooper
2016-06-21 6:19 ` Wu, Feng
2016-06-21 7:17 ` Jan Beulich
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