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From: kbuild test robot <lkp@intel.com>
To: Pavel Tatashin <pasha.tatashin@soleen.com>
Cc: mark.rutland@arm.com, catalin.marinas@arm.com, stefan@agner.ch,
	linux@armlinux.org.uk, yamada.masahiro@socionext.com,
	will@kernel.org, boris.ostrovsky@oracle.com, sashal@kernel.org,
	sstabellini@kernel.org, maz@kernel.org, jmorris@namei.org,
	linux-arm-kernel@lists.infradead.org,
	xen-devel@lists.xenproject.org, vladimir.murzin@arm.com,
	julien@xen.org, pasha.tatashin@soleen.com,
	alexios.zavras@intel.com, tglx@linutronix.de,
	allison@lohutok.net, jgross@suse.com, kbuild-all@lists.01.org,
	steve.capper@arm.com, gregkh@linuxfoundation.org,
	linux-kernel@vger.kernel.org, james.morse@arm.com,
	andrew.cooper3@citrix.com, info@metux.net
Subject: Re: [Xen-devel] [PATCH v4 3/6] arm64: remove uaccess_ttbr0 asm macros from cache functions
Date: Sun, 8 Dec 2019 04:33:40 +0800
Message-ID: <201912080035.BYa0BDRU%lkp@intel.com> (raw)
In-Reply-To: <20191204232058.2500117-4-pasha.tatashin@soleen.com>

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Hi Pavel,

Thank you for the patch! Yet something to improve:

[auto build test ERROR on next-20191206]
[cannot apply to arm64/for-next/core xen-tip/linux-next v5.4-rc8 arm/for-next v5.4]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system. BTW, we also suggest to use '--base' option to specify the
base tree in git format-patch, please see https://stackoverflow.com/a/37406982]

url:    https://github.com/0day-ci/linux/commits/Pavel-Tatashin/Use-C-inlines-for-uaccess/20191207-044947
base:    838333c80c4f64a4ef9f5486f8bbc73312cd3abf
config: arm64-defconfig (attached as .config)
compiler: aarch64-linux-gcc (GCC) 7.5.0
reproduce:
        wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # save the attached .config to linux build tree
        GCC_VERSION=7.5.0 make.cross ARCH=arm64 

If you fix the issue, kindly add following tag
Reported-by: kbuild test robot <lkp@intel.com>

All errors (new ones prefixed by >>):

   arch/arm64/kernel/sys_compat.c: In function '__do_compat_cache_op':
>> arch/arm64/kernel/sys_compat.c:44:7: error: void value not ignored as it ought to be
      ret = __flush_cache_user_range(start, start + chunk);
          ^

vim +44 arch/arm64/kernel/sys_compat.c

3dd681d944f6d8 Will Deacon     2012-03-05  23  
a2d25a5391ca21 Vladimir Murzin 2014-12-01  24  static long
a2d25a5391ca21 Vladimir Murzin 2014-12-01  25  __do_compat_cache_op(unsigned long start, unsigned long end)
3dd681d944f6d8 Will Deacon     2012-03-05  26  {
a2d25a5391ca21 Vladimir Murzin 2014-12-01  27  	long ret;
3dd681d944f6d8 Will Deacon     2012-03-05  28  
a2d25a5391ca21 Vladimir Murzin 2014-12-01  29  	do {
a2d25a5391ca21 Vladimir Murzin 2014-12-01  30  		unsigned long chunk = min(PAGE_SIZE, end - start);
3dd681d944f6d8 Will Deacon     2012-03-05  31  
a2d25a5391ca21 Vladimir Murzin 2014-12-01  32  		if (fatal_signal_pending(current))
a2d25a5391ca21 Vladimir Murzin 2014-12-01  33  			return 0;
a2d25a5391ca21 Vladimir Murzin 2014-12-01  34  
222fc0c8503d98 James Morse     2019-10-17  35  		if (cpus_have_const_cap(ARM64_WORKAROUND_1542419)) {
222fc0c8503d98 James Morse     2019-10-17  36  			/*
222fc0c8503d98 James Morse     2019-10-17  37  			 * The workaround requires an inner-shareable tlbi.
222fc0c8503d98 James Morse     2019-10-17  38  			 * We pick the reserved-ASID to minimise the impact.
222fc0c8503d98 James Morse     2019-10-17  39  			 */
27a22fbdeedd6c Catalin Marinas 2019-10-28  40  			__tlbi(aside1is, __TLBI_VADDR(0, 0));
222fc0c8503d98 James Morse     2019-10-17  41  			dsb(ish);
222fc0c8503d98 James Morse     2019-10-17  42  		}
222fc0c8503d98 James Morse     2019-10-17  43  
a2d25a5391ca21 Vladimir Murzin 2014-12-01 @44  		ret = __flush_cache_user_range(start, start + chunk);
a2d25a5391ca21 Vladimir Murzin 2014-12-01  45  		if (ret)
a2d25a5391ca21 Vladimir Murzin 2014-12-01  46  			return ret;
a2d25a5391ca21 Vladimir Murzin 2014-12-01  47  
a2d25a5391ca21 Vladimir Murzin 2014-12-01  48  		cond_resched();
a2d25a5391ca21 Vladimir Murzin 2014-12-01  49  		start += chunk;
a2d25a5391ca21 Vladimir Murzin 2014-12-01  50  	} while (start < end);
a2d25a5391ca21 Vladimir Murzin 2014-12-01  51  
a2d25a5391ca21 Vladimir Murzin 2014-12-01  52  	return 0;
3dd681d944f6d8 Will Deacon     2012-03-05  53  }
3dd681d944f6d8 Will Deacon     2012-03-05  54  

:::::: The code at line 44 was first introduced by commit
:::::: a2d25a5391ca219f196f9fee7b535c40d201c6bf arm64: compat: align cacheflush syscall with arch/arm

:::::: TO: Vladimir Murzin <vladimir.murzin@arm.com>
:::::: CC: Will Deacon <will.deacon@arm.com>

---
0-DAY kernel test infrastructure                 Open Source Technology Center
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org Intel Corporation

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Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-12-04 23:20 [Xen-devel] [PATCH v4 0/6] Use C inlines for uaccess Pavel Tatashin
2019-12-04 23:20 ` [Xen-devel] [PATCH v4 1/6] arm/arm64/xen: hypercall.h add includes guards Pavel Tatashin
2019-12-16 20:36   ` Julien Grall
2019-12-18 21:11     ` Pavel Tatashin
2019-12-04 23:20 ` [Xen-devel] [PATCH v4 2/6] arm/arm64/xen: use C inlines for privcmd_call Pavel Tatashin
2019-12-16 20:41   ` Julien Grall
2019-12-18 21:11     ` Pavel Tatashin
2019-12-04 23:20 ` [Xen-devel] [PATCH v4 3/6] arm64: remove uaccess_ttbr0 asm macros from cache functions Pavel Tatashin
2019-12-07 20:33   ` kbuild test robot [this message]
2019-12-04 23:20 ` [Xen-devel] [PATCH v4 4/6] arm64: remove __asm_flush_icache_range Pavel Tatashin
2019-12-04 23:20 ` [Xen-devel] [PATCH v4 5/6] arm64: move ARM64_HAS_CACHE_DIC/_IDC from asm to C Pavel Tatashin
2019-12-04 23:20 ` [Xen-devel] [PATCH v4 6/6] arm64: remove the rest of asm-uaccess.h Pavel Tatashin

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