From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-0.7 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4A88FC433E1 for ; Wed, 17 Jun 2020 09:10:11 +0000 (UTC) Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 2628F2070A for ; Wed, 17 Jun 2020 09:10:11 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 2628F2070A Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=citrix.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1jlU4t-00061U-NI; Wed, 17 Jun 2020 09:09:51 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57] helo=us1-amaz-eas2.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1jlU4s-00061P-Vp for xen-devel@lists.xenproject.org; Wed, 17 Jun 2020 09:09:51 +0000 X-Inumbo-ID: 4c1696b8-b07a-11ea-b9ae-12813bfff9fa Received: from esa2.hc3370-68.iphmx.com (unknown [216.71.145.153]) by us1-amaz-eas2.inumbo.com (Halon) with ESMTPS id 4c1696b8-b07a-11ea-b9ae-12813bfff9fa; Wed, 17 Jun 2020 09:09:50 +0000 (UTC) Authentication-Results: esa2.hc3370-68.iphmx.com; dkim=none (message not signed) header.i=none IronPort-SDR: 2Ga5Ehl2ycOHUWmP6oHZ+QWITf7JVhV5CW0cohm862hmWIaZSU9gnW6p+X3Xh2MxK5Y7NLtGq4 jTMEAqUU94W+fofCGiq5piCeyxthkYN8VDrymV4/u9asg9eat3WwDiC9eGab2BasBM4XFERv1E bneHhbW/v/UEofkRf7jaAemOXv+YJp6Q6RdEU39GL3AvxmmxcxVxVv2MsXY6DpDnwT4BENlA/F v1GS8PH6PzIifqEbP2P1m2mLdbvULG0qfn1F2+slZJthS504ReM8reLMyvB0SBbdgveB8RO+dm Dq4= X-SBRS: 2.7 X-MesageID: 20263476 X-Ironport-Server: esa2.hc3370-68.iphmx.com X-Remote-IP: 162.221.158.21 X-Policy: $RELAYED X-IronPort-AV: E=Sophos;i="5.73,522,1583211600"; d="scan'208";a="20263476" Date: Wed, 17 Jun 2020 11:09:42 +0200 From: Roger Pau =?utf-8?B?TW9ubsOp?= To: =?utf-8?Q?Micha=C5=82_Leszczy=C5=84ski?= Subject: Re: [PATCH v1 7/7] x86/vmx: switch IPT MSRs on vmentry/vmexit Message-ID: <20200617090942.GY735@Air-de-Roger> References: <1548605014.8764792.1592320576239.JavaMail.zimbra@cert.pl> <317430261.8766476.1592321051337.JavaMail.zimbra@cert.pl> <20200616173857.GU735@Air-de-Roger> <676696113.8782412.1592329627666.JavaMail.zimbra@cert.pl> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <676696113.8782412.1592329627666.JavaMail.zimbra@cert.pl> X-ClientProxiedBy: AMSPEX02CAS02.citrite.net (10.69.22.113) To AMSPEX02CL02.citrite.net (10.69.22.126) X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Kevin Tian , Jun Nakajima , Wei Liu , Andrew Cooper , Jan Beulich , Xen-devel Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" On Tue, Jun 16, 2020 at 07:47:07PM +0200, Michał Leszczyński wrote: > ----- 16 cze 2020 o 19:38, Roger Pau Monné roger.pau@citrix.com napisał(a): > > > On Tue, Jun 16, 2020 at 05:24:11PM +0200, Michał Leszczyński wrote: > >> Enable IPT when entering the VM and disable it on vmexit. > >> Register state is persisted using vCPU ipt_state structure. > > > > Shouldn't this be better done using Intel MSR load lists? > > > > That seems to be what the SDM recommends for tracing VM events. > > > > Thanks, Roger. > > > This is intentional, additionally described by the comment: > > // MSR_IA32_RTIT_CTL is context-switched manually instead of being > // stored inside VMCS, as of Q2'20 only the most recent processors > // support such field in VMCS > > > There is a special feature flag which indicates whether MSR_IA32_RTIT_CTL can be loaded using MR load lists. I've been looking at the Intel SDM and I'm not able to find which bit signals whether MSR_IA32_RTIT_CTL can be loaded using MSR load lists. Sorry to ask, but can you elaborate on where is this signaled? Thanks, Roger.