From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 06461C433ED for ; Tue, 20 Apr 2021 07:09:33 +0000 (UTC) Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id AC7A6611F2 for ; Tue, 20 Apr 2021 07:09:32 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org AC7A6611F2 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from list by lists.xenproject.org with outflank-mailman.113312.215954 (Exim 4.92) (envelope-from ) id 1lYkVh-0006dH-Ec; Tue, 20 Apr 2021 07:09:25 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 113312.215954; Tue, 20 Apr 2021 07:09:25 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1lYkVh-0006d8-9n; Tue, 20 Apr 2021 07:09:25 +0000 Received: by outflank-mailman (input) for mailman id 113312; Tue, 20 Apr 2021 07:09:23 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57] helo=us1-amaz-eas2.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1lYkVf-0006Ja-Nh for xen-devel@lists.xenproject.org; Tue, 20 Apr 2021 07:09:23 +0000 Received: from foss.arm.com (unknown [217.140.110.172]) by us1-amaz-eas2.inumbo.com (Halon) with ESMTP id 8d41fb0d-5c6c-4ba9-9ceb-8412447acf09; Tue, 20 Apr 2021 07:09:11 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id B40481474; Tue, 20 Apr 2021 00:09:10 -0700 (PDT) Received: from e123311-lin.arm.com (unknown [10.57.29.239]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 9EC213F85F; Tue, 20 Apr 2021 00:09:09 -0700 (PDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 8d41fb0d-5c6c-4ba9-9ceb-8412447acf09 From: Michal Orzel To: xen-devel@lists.xenproject.org Cc: Stefano Stabellini , Julien Grall , Volodymyr Babchuk , bertrand.marquis@arm.com Subject: [PATCH 4/9] arm/p2m: Get rid of READ/WRITE_SYSREG32 Date: Tue, 20 Apr 2021 09:08:48 +0200 Message-Id: <20210420070853.8918-5-michal.orzel@arm.com> X-Mailer: git-send-email 2.29.0 In-Reply-To: <20210420070853.8918-1-michal.orzel@arm.com> References: <20210420070853.8918-1-michal.orzel@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit AArch64 system registers are 64bit whereas AArch32 ones are 32bit or 64bit. MSR/MRS are expecting 64bit values thus we should get rid of helpers READ/WRITE_SYSREG32 in favour of using READ/WRITE_SYSREG. We should also use register_t type when reading sysregs which can correspond to uint64_t or uint32_t. Even though many AArch64 sysregs have upper 32bit reserved it does not mean that they can't be widen in the future. Modify type of vtcr to register_t. Signed-off-by: Michal Orzel --- xen/arch/arm/p2m.c | 8 ++++---- xen/arch/arm/traps.c | 2 +- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/xen/arch/arm/p2m.c b/xen/arch/arm/p2m.c index ac50312620..d414c4feb9 100644 --- a/xen/arch/arm/p2m.c +++ b/xen/arch/arm/p2m.c @@ -1973,11 +1973,11 @@ void __init p2m_restrict_ipa_bits(unsigned int ipa_bits) } /* VTCR value to be configured by all CPUs. Set only once by the boot CPU */ -static uint32_t __read_mostly vtcr; +static register_t __read_mostly vtcr; static void setup_virt_paging_one(void *data) { - WRITE_SYSREG32(vtcr, VTCR_EL2); + WRITE_SYSREG(vtcr, VTCR_EL2); /* * ARM64_WORKAROUND_AT_SPECULATE: We want to keep the TLBs free from @@ -2000,7 +2000,7 @@ static void setup_virt_paging_one(void *data) void __init setup_virt_paging(void) { /* Setup Stage 2 address translation */ - unsigned long val = VTCR_RES1|VTCR_SH0_IS|VTCR_ORGN0_WBWA|VTCR_IRGN0_WBWA; + register_t val = VTCR_RES1|VTCR_SH0_IS|VTCR_ORGN0_WBWA|VTCR_IRGN0_WBWA; #ifdef CONFIG_ARM_32 if ( p2m_ipa_bits < 40 ) @@ -2089,7 +2089,7 @@ void __init setup_virt_paging(void) pa_range_info[pa_range].pabits, ( MAX_VMID == MAX_VMID_16_BIT ) ? 16 : 8); #endif - printk("P2M: %d levels with order-%d root, VTCR 0x%lx\n", + printk("P2M: %d levels with order-%d root, VTCR 0x%"PRIregister"\n", 4 - P2M_ROOT_LEVEL, P2M_ROOT_ORDER, val); p2m_vmid_allocator_init(); diff --git a/xen/arch/arm/traps.c b/xen/arch/arm/traps.c index ccc0827107..c7acdb2087 100644 --- a/xen/arch/arm/traps.c +++ b/xen/arch/arm/traps.c @@ -911,7 +911,7 @@ static void _show_registers(const struct cpu_user_regs *regs, show_registers_32(regs, ctxt, guest_mode, v); #endif } - printk(" VTCR_EL2: %08"PRIx32"\n", READ_SYSREG32(VTCR_EL2)); + printk(" VTCR_EL2: %"PRIregister"\n", READ_SYSREG(VTCR_EL2)); printk(" VTTBR_EL2: %016"PRIx64"\n", ctxt->vttbr_el2); printk("\n"); -- 2.29.0