From: Jan Beulich <jbeulich@suse.com>
To: "xen-devel@lists.xenproject.org" <xen-devel@lists.xenproject.org>
Cc: "Andrew Cooper" <andrew.cooper3@citrix.com>,
"Wei Liu" <wl@xen.org>, "Roger Pau Monné" <roger.pau@citrix.com>
Subject: [PATCH v3] x86/PV: remove unnecessary toggle_guest_pt() overhead
Date: Tue, 5 May 2020 08:16:03 +0200 [thread overview]
Message-ID: <24d8b606-f74b-9367-d67e-e952838c7048@suse.com> (raw)
While the mere updating of ->pv_cr3 and ->root_pgt_changed aren't overly
expensive (but still needed only for the toggle_guest_mode() path), the
effect of the latter on the exit-to-guest path is not insignificant.
Move the logic into toggle_guest_mode(), on the basis that
toggle_guest_pt() will always be invoked in pairs, yet we can't safely
undo the setting of root_pgt_changed during the second of these
invocations.
While at it, add a comment ahead of toggle_guest_pt() to clarify its
intended usage.
Signed-off-by: Jan Beulich <jbeulich@suse.com>
---
v3: Add comment ahead of toggle_guest_pt().
v2: Extend description.
--- a/xen/arch/x86/pv/domain.c
+++ b/xen/arch/x86/pv/domain.c
@@ -393,18 +393,10 @@ bool __init xpti_pcid_enabled(void)
static void _toggle_guest_pt(struct vcpu *v)
{
- const struct domain *d = v->domain;
- struct cpu_info *cpu_info = get_cpu_info();
unsigned long cr3;
v->arch.flags ^= TF_kernel_mode;
update_cr3(v);
- if ( d->arch.pv.xpti )
- {
- cpu_info->root_pgt_changed = true;
- cpu_info->pv_cr3 = __pa(this_cpu(root_pgt)) |
- (d->arch.pv.pcid ? get_pcid_bits(v, true) : 0);
- }
/*
* Don't flush user global mappings from the TLB. Don't tick TLB clock.
@@ -412,15 +404,11 @@ static void _toggle_guest_pt(struct vcpu
* In shadow mode, though, update_cr3() may need to be accompanied by a
* TLB flush (for just the incoming PCID), as the top level page table may
* have changed behind our backs. To be on the safe side, suppress the
- * no-flush unconditionally in this case. The XPTI CR3 write, if enabled,
- * will then need to be a flushing one too.
+ * no-flush unconditionally in this case.
*/
cr3 = v->arch.cr3;
- if ( shadow_mode_enabled(d) )
- {
+ if ( shadow_mode_enabled(v->domain) )
cr3 &= ~X86_CR3_NOFLUSH;
- cpu_info->pv_cr3 &= ~X86_CR3_NOFLUSH;
- }
write_cr3(cr3);
if ( !(v->arch.flags & TF_kernel_mode) )
@@ -436,6 +424,8 @@ static void _toggle_guest_pt(struct vcpu
void toggle_guest_mode(struct vcpu *v)
{
+ const struct domain *d = v->domain;
+
ASSERT(!is_pv_32bit_vcpu(v));
/* %fs/%gs bases can only be stale if WR{FS,GS}BASE are usable. */
@@ -449,8 +439,27 @@ void toggle_guest_mode(struct vcpu *v)
asm volatile ( "swapgs" );
_toggle_guest_pt(v);
+
+ if ( d->arch.pv.xpti )
+ {
+ struct cpu_info *cpu_info = get_cpu_info();
+
+ cpu_info->root_pgt_changed = true;
+ cpu_info->pv_cr3 = __pa(this_cpu(root_pgt)) |
+ (d->arch.pv.pcid ? get_pcid_bits(v, true) : 0);
+ /*
+ * As in _toggle_guest_pt() the XPTI CR3 write needs to be a TLB-
+ * flushing one too for shadow mode guests.
+ */
+ if ( shadow_mode_enabled(d) )
+ cpu_info->pv_cr3 &= ~X86_CR3_NOFLUSH;
+ }
}
+/*
+ * Must be called in matching pairs without returning to guest context
+ * inbetween.
+ */
void toggle_guest_pt(struct vcpu *v)
{
if ( !is_pv_32bit_vcpu(v) )
next reply other threads:[~2020-05-05 6:16 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-05-05 6:16 Jan Beulich [this message]
2020-05-18 16:52 ` [PATCH v3] x86/PV: remove unnecessary toggle_guest_pt() overhead Roger Pau Monné
2020-05-21 16:46 ` Andrew Cooper
2020-05-22 10:07 ` Jan Beulich
2020-05-29 16:24 ` Andrew Cooper
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