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From: Julien Grall <julien.grall@arm.com>
To: Stefano Stabellini <sstabellini@kernel.org>
Cc: xen-devel@lists.xenproject.org
Subject: Re: [PATCH for-4.12 v2 15/17] xen/arm: p2m: Add support for preemption in p2m_cache_flush_range
Date: Fri, 7 Dec 2018 11:15:43 +0000	[thread overview]
Message-ID: <2c917b48-9205-11f8-b9ac-313f242c7f97@arm.com> (raw)
In-Reply-To: <alpine.DEB.2.10.1812061516050.18779@sstabellini-ThinkPad-X260>

Hi Stefano,

On 06/12/2018 23:32, Stefano Stabellini wrote:
> On Tue, 4 Dec 2018, Julien Grall wrote:
>> p2m_cache_flush_range does not yet support preemption, this may be an
>> issue as cleaning the cache can take a long time. While the current
>> caller (XEN_DOMCTL_cacheflush) does not stricly require preemption, this
>> will be necessary for new caller in a follow-up patch.
>>
>> The preemption implemented is quite simple, a counter is incremented by:
>>      - 1 on region skipped
>>      - 10 for each page requiring a flush
>>
>> When the counter reach 512 or above, we will check if preemption is
>> needed. If not, the counter will be reset to 0. If yes, the function
>> will stop, update start (to allow resuming later on) and return
>> -ERESTART. This allows the caller to decide how the preemption will be
>> done.
>>
>> For now, XEN_DOMCTL_cacheflush will continue to ignore the preemption.
>>
>> Signed-off-by: Julien Grall <julien.grall@arm.com>
>>
>> ---
>>      Changes in v2:
>>          - Patch added
>> ---
>>   xen/arch/arm/domctl.c     |  8 +++++++-
>>   xen/arch/arm/p2m.c        | 35 ++++++++++++++++++++++++++++++++---
>>   xen/include/asm-arm/p2m.h |  4 +++-
>>   3 files changed, 42 insertions(+), 5 deletions(-)
>>
>> diff --git a/xen/arch/arm/domctl.c b/xen/arch/arm/domctl.c
>> index 20691528a6..9da88b8c64 100644
>> --- a/xen/arch/arm/domctl.c
>> +++ b/xen/arch/arm/domctl.c
>> @@ -54,6 +54,7 @@ long arch_do_domctl(struct xen_domctl *domctl, struct domain *d,
>>       {
>>           gfn_t s = _gfn(domctl->u.cacheflush.start_pfn);
>>           gfn_t e = gfn_add(s, domctl->u.cacheflush.nr_pfns);
>> +        int rc;
> 
> This is unnecessary...
> 
> 
>>           if ( domctl->u.cacheflush.nr_pfns > (1U<<MAX_ORDER) )
>>               return -EINVAL;
>> @@ -61,7 +62,12 @@ long arch_do_domctl(struct xen_domctl *domctl, struct domain *d,
>>           if ( gfn_x(e) < gfn_x(s) )
>>               return -EINVAL;
>>   
>> -        return p2m_cache_flush_range(d, s, e);
>> +        /* XXX: Handle preemption */
>> +        do
>> +            rc = p2m_cache_flush_range(d, &s, e);
>> +        while ( rc == -ERESTART );
> 
> ... you can just do:
> 
>    while ( -ERESTART == p2m_cache_flush_range(d, &s, e) )
> 
> But given that it is just style, I'll leave it up to you.

I don't much like the idea to have the loop body empty. This is error-prone 
depending where you use do {} while (...) or while ( ... );

So I would prefer to stick with a temporary variable.

> 
> 
>> +        return rc;
>>       }
>>       case XEN_DOMCTL_bind_pt_irq:
>>       {
>> diff --git a/xen/arch/arm/p2m.c b/xen/arch/arm/p2m.c
>> index db22b53bfd..ca9f0d9ebe 100644
>> --- a/xen/arch/arm/p2m.c
>> +++ b/xen/arch/arm/p2m.c
>> @@ -1524,13 +1524,17 @@ int relinquish_p2m_mapping(struct domain *d)
>>       return rc;
>>   }
>>   
>> -int p2m_cache_flush_range(struct domain *d, gfn_t start, gfn_t end)
>> +int p2m_cache_flush_range(struct domain *d, gfn_t *pstart, gfn_t end)
>>   {
>>       struct p2m_domain *p2m = p2m_get_hostp2m(d);
>>       gfn_t next_block_gfn;
>> +    gfn_t start = *pstart;
>>       mfn_t mfn = INVALID_MFN;
>>       p2m_type_t t;
>>       unsigned int order;
>> +    int rc = 0;
>> +    /* Counter for preemption */
>> +    unsigned long count = 0;
>>   
>>       /*
>>        * The operation cache flush will invalidate the RAM assigned to the
>> @@ -1547,6 +1551,25 @@ int p2m_cache_flush_range(struct domain *d, gfn_t start, gfn_t end)
>>   
>>       while ( gfn_x(start) < gfn_x(end) )
>>       {
>> +       /*
>> +         * Cleaning the cache for the P2M may take a long time. So we
>> +         * need to be able to preempt. We will arbitrarily preempt every
>> +         * time count reach 512 or above.
>> +
>> +         *
>> +         * The count will be incremented by:
>> +         *  - 1 on region skipped
>> +         *  - 10 for each page requiring a flush
> 
> Why this choice? A page flush should cost much more than 10x a region
> skipped, more like 100x or 1000x. In fact, doing the full loop without
> calling flush_page_to_ram should be cheap and fast, right?.

It is cheaper than a flush of the page but it still has a cost. You have to walk 
the stage-2 in software that will require to map the tables. As all the memory 
is not mapped in the hypervisor on arm32 this will require a map/unmap 
operation. On arm64, so far the full memory is mapped, so the map/unmap is 
pretty much a NOP.

> I would:
> 
> - not increase count on region skipped at all
> - increase it by 1 on each page requiring a flush
> - set the limit lower, if we go with your proposal it would be about 50,
>    I am not sure what the limit should be though
I don't think you can avoid incrementing count on region skipped. While one 
lookup is pretty cheap, all the lookups for hole added together may result to a 
pretty long time.

Even if stage-2 mappings are handled by the hypervisor, the guest is still 
somewhat in control of it because it can balloon in/out pages. The operation may 
result to shatter stage-2 mappings.

It would be feasible for a guest to shatter 1GB of memory in 4KB mappings in 
stage-2 entries and then remove all the entries. This means the stage-2 would 
contains 262144 holes. This would result to 262144 iterations, so no matter how 
cheap it is the resulting time spent without preemption is going to be quite 
important.

The choice in the numbers 1 vs 10 is pretty much random. The question is how 
often we want to check for pending softirq. The check is pretty much trivial, 
yet it has a cost to preempt. With the current solution, we check preemption 
every 512 holes or 51 pages flushed (~204KB flushed).

This sounds ok to me. Feel free to suggest better number.

> 
> 
>> +         */
>> +        if ( count >= 512 )
>> +        {
>> +            if ( softirq_pending(smp_processor_id()) )
>> +            {
>> +                rc = -ERESTART;
>> +                break;
>> +            }
>> +            count = 0;
> 
> No need to set count to 0 here

Well, the code would not do the same here. If you don't reset to 0, you would 
check softirq_pending() all the iteration when count reached 512.

If you reset 0, you will avoid to check softirq_pending() until the next time 
count reached 512.

The both are actually valid. It just a matter on whether we are assuming that a 
softirq will happen soon after reaching 512?

> 
> 
>> +        }
>> +
>>           /*
>>            * We want to flush page by page as:
>>            *  - it may not be possible to map the full block (can be up to 1GB)
>> @@ -1573,22 +1596,28 @@ int p2m_cache_flush_range(struct domain *d, gfn_t start, gfn_t end)
>>                */
>>               if ( mfn_eq(mfn, INVALID_MFN) || !p2m_is_any_ram(t) )
>>               {
>> +                count++;
> 
> This is just an iteration doing nothing, I would not increament count.

[...]

> This makes sense, but if we skip the count++ above, we might as well
> just count++ here and have a lower limit.

See above for why I think this can't work.

Cheers,

-- 
Julien Grall

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  reply	other threads:[~2018-12-07 11:15 UTC|newest]

Thread overview: 53+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-12-04 20:26 [PATCH for-4.12 v2 00/17] xen/arm: Implement Set/Way operations Julien Grall
2018-12-04 20:26 ` [PATCH for-4.12 v2 01/17] xen/arm: Introduce helpers to clear/flags flags in HCR_EL2 Julien Grall
2018-12-04 20:26 ` [PATCH for-4.12 v2 02/17] xen/arm: traps: Move the implementation of GUEST_BUG_ON in traps.h Julien Grall
2018-12-04 20:26 ` [PATCH for-4.12 v2 03/17] xen/arm: p2m: Clean-up headers included and order them alphabetically Julien Grall
2018-12-04 23:47   ` Stefano Stabellini
2018-12-04 20:26 ` [PATCH for-4.12 v2 04/17] xen/arm: p2m: Introduce p2m_is_valid and use it Julien Grall
2018-12-04 23:50   ` Stefano Stabellini
2018-12-05  9:46     ` Julien Grall
2018-12-06 22:02       ` Stefano Stabellini
2018-12-07 10:14         ` Julien Grall
2018-12-04 20:26 ` [PATCH for-4.12 v2 05/17] xen/arm: p2m: Handle translation fault in get_page_from_gva Julien Grall
2018-12-04 23:59   ` Stefano Stabellini
2018-12-05 10:03     ` Julien Grall
2018-12-06 22:04       ` Stefano Stabellini
2018-12-07 10:16         ` Julien Grall
2018-12-07 16:56           ` Stefano Stabellini
2018-12-04 20:26 ` [PATCH for-4.12 v2 06/17] xen/arm: p2m: Introduce a function to resolve translation fault Julien Grall
2018-12-06 22:33   ` Stefano Stabellini
2018-12-04 20:26 ` [PATCH for-4.12 v2 07/17] xen/arm: vcpreg: Add wrappers to handle co-proc access trapped by HCR_EL2.TVM Julien Grall
2018-12-06 22:33   ` Stefano Stabellini
2018-12-04 20:26 ` [PATCH for-4.12 v2 08/17] xen/arm: vsysreg: Add wrapper to handle sysreg " Julien Grall
2018-12-04 20:26 ` [PATCH for-4.12 v2 09/17] xen/arm: Rework p2m_cache_flush to take a range [begin, end) Julien Grall
2018-12-04 20:26 ` [PATCH for-4.12 v2 10/17] xen/arm: p2m: Allow to flush cache on any RAM region Julien Grall
2018-12-04 20:26 ` [PATCH for-4.12 v2 11/17] xen/arm: p2m: Extend p2m_get_entry to return the value of bit[0] (valid bit) Julien Grall
2018-12-04 20:35   ` Razvan Cojocaru
2018-12-06 22:32     ` Stefano Stabellini
2018-12-07 10:17     ` Julien Grall
2018-12-04 20:26 ` [PATCH for-4.12 v2 12/17] xen/arm: traps: Rework leave_hypervisor_tail Julien Grall
2018-12-06 23:08   ` Stefano Stabellini
2018-12-04 20:26 ` [PATCH for-4.12 v2 13/17] xen/arm: p2m: Rework p2m_cache_flush_range Julien Grall
2018-12-06 23:53   ` Stefano Stabellini
2018-12-07 10:18     ` Julien Grall
2018-12-04 20:26 ` [PATCH for-4.12 v2 14/17] xen/arm: domctl: Use typesafe gfn in XEN_DOMCTL_cacheflush Julien Grall
2018-12-06 23:13   ` Stefano Stabellini
2018-12-04 20:26 ` [PATCH for-4.12 v2 15/17] xen/arm: p2m: Add support for preemption in p2m_cache_flush_range Julien Grall
2018-12-06 23:32   ` Stefano Stabellini
2018-12-07 11:15     ` Julien Grall [this message]
2018-12-07 22:11       ` Stefano Stabellini
2018-12-11 16:11         ` Julien Grall
2018-12-04 20:26 ` [PATCH for-4.12 v2 16/17] xen/arm: Implement Set/Way operations Julien Grall
2018-12-06 23:32   ` Stefano Stabellini
2018-12-07 13:22     ` Julien Grall
2018-12-07 21:29       ` Stefano Stabellini
2018-12-12 15:33         ` Julien Grall
2018-12-12 17:25           ` Stefano Stabellini
2018-12-12 17:49             ` Dario Faggioli
2018-12-04 20:26 ` [PATCH for-4.12 v2 17/17] xen/arm: Track page accessed between batch of " Julien Grall
2018-12-05  8:37   ` Jan Beulich
2018-12-07 13:24     ` Julien Grall
2018-12-06 12:21   ` Julien Grall
2018-12-07 21:52     ` Stefano Stabellini
2018-12-07 21:43   ` Stefano Stabellini
2018-12-11 16:22     ` Julien Grall

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