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X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Apr 2023 07:21:42.5381 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 35a1f825-7cb3-4fb7-0d0c-08db3f1464c9 X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d;Ip=[63.35.35.123];Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: DBAEUR03FT007.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: VI1PR08MB5328 > On 16 Apr 2023, at 15:32, Julien Grall wrote: >=20 > From: Julien Grall >=20 > Xen is currently not fully compliant with the Arm Arm because it will > switch the TTBR with the MMU on. >=20 > In order to be compliant, we need to disable the MMU before > switching the TTBR. The implication is the page-tables should > contain an identity mapping of the code switching the TTBR. >=20 > In most of the case we expect Xen to be loaded in low memory. I am aware > of one platform (i.e AMD Seattle) where the memory start above 512GB. > To give us some slack, consider that Xen may be loaded in the first 2TB > of the physical address space. >=20 > The memory layout is reshuffled to keep the first four slots of the zeroe= th > level free. All the regions currently in L0 slot 0 will not be part of > slot 4 (2TB). This requires a slight tweak of the boot code because > XEN_VIRT_START (2TB + 2MB) cannot be used as an immediate. >=20 > This reshuffle will make trivial to create a 1:1 mapping when Xen is > loaded below 2TB. >=20 > Lastly, take the opportunity to check a compile time if any of the > regions may overlap with the reserved area for identity mapping. >=20 > Signed-off-by: Julien Grall >=20 Hi Julien, It looks fine to me. Reviewed-by: Luca Fancellu