From mboxrd@z Thu Jan 1 00:00:00 1970 From: "Jan Beulich" Subject: [PATCH v3 09/10] VT-d: use qword MMIO access for MSI address writes Date: Fri, 05 Jun 2015 12:26:07 +0100 Message-ID: <5571A36F02000078000814C6@mail.emea.novell.com> References: <55719F9D0200007800081425@mail.emea.novell.com> Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="=__Part94A0BD5F.1__=" Return-path: Received: from mail6.bemta14.messagelabs.com ([193.109.254.103]) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1Z0plJ-0004Ny-2m for xen-devel@lists.xenproject.org; Fri, 05 Jun 2015 11:26:09 +0000 In-Reply-To: <55719F9D0200007800081425@mail.emea.novell.com> List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org To: xen-devel Cc: Yang Z Zhang , Kevin Tian List-Id: xen-devel@lists.xenproject.org This is a MIME message. If you are reading this text, you may want to consider changing to a mail reader or gateway that understands how to properly handle MIME multipart messages. --=__Part94A0BD5F.1__= Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: quoted-printable Content-Disposition: inline Also make dmar_{read,write}q() actually do what their names suggest (we don't need to be concerned of 32-bit restrictions anymore). Signed-off-by: Jan Beulich --- a/xen/drivers/passthrough/vtd/iommu.c +++ b/xen/drivers/passthrough/vtd/iommu.c @@ -1054,8 +1054,7 @@ static void dma_msi_set_affinity(struct=20 =20 spin_lock_irqsave(&iommu->register_lock, flags); dmar_writel(iommu->reg, DMAR_FEDATA_REG, msg.data); - dmar_writel(iommu->reg, DMAR_FEADDR_REG, msg.address_lo); - dmar_writel(iommu->reg, DMAR_FEUADDR_REG, msg.address_hi); + dmar_writeq(iommu->reg, DMAR_FEADDR_REG, msg.address); spin_unlock_irqrestore(&iommu->register_lock, flags); } =20 --- a/xen/drivers/passthrough/vtd/iommu.h +++ b/xen/drivers/passthrough/vtd/iommu.h @@ -51,17 +51,10 @@ #define DMAR_IRTA_REG 0xB8 /* intr remap */ =20 #define OFFSET_STRIDE (9) -#define dmar_readl(dmar, reg) readl(dmar + reg) -#define dmar_writel(dmar, reg, val) writel(val, dmar + reg) -#define dmar_readq(dmar, reg) ({ \ - u32 lo, hi; \ - lo =3D dmar_readl(dmar, reg); \ - hi =3D dmar_readl(dmar, reg + 4); \ - (((u64) hi) << 32) + lo; }) -#define dmar_writeq(dmar, reg, val) do {\ - dmar_writel(dmar, reg, (u32)val); \ - dmar_writel(dmar, reg + 4, (u32)((u64) val >> 32)); \ - } while (0) +#define dmar_readl(dmar, reg) readl((dmar) + (reg)) +#define dmar_readq(dmar, reg) readq((dmar) + (reg)) +#define dmar_writel(dmar, reg, val) writel(val, (dmar) + (reg)) +#define dmar_writeq(dmar, reg, val) writeq(val, (dmar) + (reg)) =20 #define VER_MAJOR(v) (((v) & 0xf0) >> 4) #define VER_MINOR(v) ((v) & 0x0f) --=__Part94A0BD5F.1__= Content-Type: text/plain; name="VT-d-MMIO-qword.patch" Content-Transfer-Encoding: quoted-printable Content-Disposition: attachment; filename="VT-d-MMIO-qword.patch" VT-d: use qword MMIO access for MSI address writes=0A=0AAlso make = dmar_{read,write}q() actually do what their names suggest (we=0Adon#t need = to be concerned of 32-bit restrictions anymore).=0A=0ASigned-off-by: Jan = Beulich =0A=0A--- a/xen/drivers/passthrough/vtd/iommu.c= =0A+++ b/xen/drivers/passthrough/vtd/iommu.c=0A@@ -1054,8 +1054,7 @@ = static void dma_msi_set_affinity(struct =0A =0A spin_lock_irqsave(&iomm= u->register_lock, flags);=0A dmar_writel(iommu->reg, DMAR_FEDATA_REG, = msg.data);=0A- dmar_writel(iommu->reg, DMAR_FEADDR_REG, msg.address_lo);= =0A- dmar_writel(iommu->reg, DMAR_FEUADDR_REG, msg.address_hi);=0A+ = dmar_writeq(iommu->reg, DMAR_FEADDR_REG, msg.address);=0A spin_unlock_i= rqrestore(&iommu->register_lock, flags);=0A }=0A =0A--- a/xen/drivers/passt= hrough/vtd/iommu.h=0A+++ b/xen/drivers/passthrough/vtd/iommu.h=0A@@ -51,17 = +51,10 @@=0A #define DMAR_IRTA_REG 0xB8 /* intr remap */=0A =0A = #define OFFSET_STRIDE (9)=0A-#define dmar_readl(dmar, reg) = readl(dmar + reg)=0A-#define dmar_writel(dmar, reg, val) writel(val, dmar = + reg)=0A-#define dmar_readq(dmar, reg) ({ \=0A- u32 lo, hi; \=0A- = lo =3D dmar_readl(dmar, reg); \=0A- hi =3D dmar_readl(dmar, = reg + 4); \=0A- (((u64) hi) << 32) + lo; })=0A-#define dmar_writeq(d= mar, reg, val) do {\=0A- dmar_writel(dmar, reg, (u32)val); \=0A- = dmar_writel(dmar, reg + 4, (u32)((u64) val >> 32)); \=0A- } while = (0)=0A+#define dmar_readl(dmar, reg) readl((dmar) + (reg))=0A+#define = dmar_readq(dmar, reg) readq((dmar) + (reg))=0A+#define dmar_writel(dmar, = reg, val) writel(val, (dmar) + (reg))=0A+#define dmar_writeq(dmar, reg, = val) writeq(val, (dmar) + (reg))=0A =0A #define VER_MAJOR(v) (((v) = & 0xf0) >> 4)=0A #define VER_MINOR(v) ((v) & 0x0f)=0A --=__Part94A0BD5F.1__= Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Disposition: inline _______________________________________________ Xen-devel mailing list Xen-devel@lists.xen.org http://lists.xen.org/xen-devel --=__Part94A0BD5F.1__=--