From mboxrd@z Thu Jan 1 00:00:00 1970 From: "Jan Beulich" Subject: [PATCH v4 RFC 5/6] x86/MSI-X: reduce fiddling with control register during restore Date: Mon, 22 Jun 2015 15:51:00 +0100 Message-ID: <55883CF40200007800087A30@mail.emea.novell.com> References: <558839ED02000078000879FE@mail.emea.novell.com> Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="=__Part516581C4.1__=" Return-path: Received: from mail6.bemta3.messagelabs.com ([195.245.230.39]) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1Z733x-0000o9-HH for xen-devel@lists.xenproject.org; Mon, 22 Jun 2015 14:51:05 +0000 In-Reply-To: <558839ED02000078000879FE@mail.emea.novell.com> List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org To: xen-devel Cc: Andrew Cooper , Keir Fraser List-Id: xen-devel@lists.xenproject.org This is a MIME message. If you are reading this text, you may want to consider changing to a mail reader or gateway that understands how to properly handle MIME multipart messages. --=__Part516581C4.1__= Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: quoted-printable Content-Disposition: inline Rather than disabling and enabling MSI-X once per vector, do it just once per device. Signed-off-by: Jan Beulich Reviewed-by: Andrew Cooper --- a/xen/arch/x86/msi.c +++ b/xen/arch/x86/msi.c @@ -1319,6 +1319,9 @@ int pci_restore_msi_state(struct pci_dev struct msi_desc *entry, *tmp; struct irq_desc *desc; struct msi_msg msg; + u8 slot =3D PCI_SLOT(pdev->devfn), func =3D PCI_FUNC(pdev->devfn); + unsigned int type =3D 0, pos =3D 0; + u16 control =3D 0; =20 ASSERT(spin_is_locked(&pcidevs_lock)); =20 @@ -1337,8 +1340,6 @@ int pci_restore_msi_state(struct pci_dev list_for_each_entry_safe( entry, tmp, &pdev->msi_list, list ) { unsigned int i =3D 0, nr =3D 1; - u16 control =3D 0; - u8 slot =3D PCI_SLOT(pdev->devfn), func =3D PCI_FUNC(pdev->devfn);= =20 irq =3D entry->irq; desc =3D &irq_desc[irq]; @@ -1355,31 +1356,38 @@ int pci_restore_msi_state(struct pci_dev pdev->seg, pdev->bus, PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn), i); spin_unlock_irqrestore(&desc->lock, flags); + if ( type =3D=3D PCI_CAP_ID_MSIX ) + pci_conf_write16(pdev->seg, pdev->bus, slot, func, + msix_control_reg(pos), + control & ~PCI_MSIX_FLAGS_ENABLE); return -EINVAL; } =20 + ASSERT(!type || type =3D=3D entry->msi_attrib.type); + pos =3D entry->msi_attrib.pos; if ( entry->msi_attrib.type =3D=3D PCI_CAP_ID_MSI ) { msi_set_enable(pdev, 0); nr =3D entry->msi.nvec; } - else if ( entry->msi_attrib.type =3D=3D PCI_CAP_ID_MSIX ) + else if ( !type && entry->msi_attrib.type =3D=3D PCI_CAP_ID_MSIX = ) { control =3D pci_conf_read16(pdev->seg, pdev->bus, slot, func, - msix_control_reg(entry->msi_attrib.p= os)); + msix_control_reg(pos)); pci_conf_write16(pdev->seg, pdev->bus, slot, func, - msix_control_reg(entry->msi_attrib.pos), + msix_control_reg(pos), control | (PCI_MSIX_FLAGS_ENABLE | PCI_MSIX_FLAGS_MASKALL)); if ( unlikely(!memory_decoded(pdev)) ) { spin_unlock_irqrestore(&desc->lock, flags); pci_conf_write16(pdev->seg, pdev->bus, slot, func, - msix_control_reg(entry->msi_attrib.pos), + msix_control_reg(pos), control & ~PCI_MSIX_FLAGS_ENABLE); return -ENXIO; } } + type =3D entry->msi_attrib.type; =20 msg =3D entry->msg; write_msi_msg(entry, &msg); @@ -1403,9 +1411,9 @@ int pci_restore_msi_state(struct pci_dev =20 spin_unlock_irqrestore(&desc->lock, flags); =20 - if ( entry->msi_attrib.type =3D=3D PCI_CAP_ID_MSI ) + if ( type =3D=3D PCI_CAP_ID_MSI ) { - unsigned int cpos =3D msi_control_reg(entry->msi_attrib.pos); + unsigned int cpos =3D msi_control_reg(pos); =20 control =3D pci_conf_read16(pdev->seg, pdev->bus, slot, func, = cpos) & ~PCI_MSI_FLAGS_QSIZE; @@ -1415,12 +1423,13 @@ int pci_restore_msi_state(struct pci_dev =20 msi_set_enable(pdev, 1); } - else if ( entry->msi_attrib.type =3D=3D PCI_CAP_ID_MSIX ) - pci_conf_write16(pdev->seg, pdev->bus, slot, func, - msix_control_reg(entry->msi_attrib.pos), - control | PCI_MSIX_FLAGS_ENABLE); } =20 + if ( type =3D=3D PCI_CAP_ID_MSIX ) + pci_conf_write16(pdev->seg, pdev->bus, slot, func, + msix_control_reg(pos), + control | PCI_MSIX_FLAGS_ENABLE); + return 0; } =20 --=__Part516581C4.1__= Content-Type: text/plain; name="x86-MSI-X-restore-once.patch" Content-Transfer-Encoding: quoted-printable Content-Disposition: attachment; filename="x86-MSI-X-restore-once.patch" x86/MSI-X: reduce fiddling with control register during restore=0A=0ARather= than disabling and enabling MSI-X once per vector, do it just=0Aonce per = device.=0A=0ASigned-off-by: Jan Beulich =0AReviewed-by: = Andrew Cooper =0A=0A--- a/xen/arch/x86/msi.c=0A+= ++ b/xen/arch/x86/msi.c=0A@@ -1319,6 +1319,9 @@ int pci_restore_msi_state(s= truct pci_dev=0A struct msi_desc *entry, *tmp;=0A struct irq_desc = *desc;=0A struct msi_msg msg;=0A+ u8 slot =3D PCI_SLOT(pdev->devfn),= func =3D PCI_FUNC(pdev->devfn);=0A+ unsigned int type =3D 0, pos =3D = 0;=0A+ u16 control =3D 0;=0A =0A ASSERT(spin_is_locked(&pcidevs_lock= ));=0A =0A@@ -1337,8 +1340,6 @@ int pci_restore_msi_state(struct pci_dev=0A= list_for_each_entry_safe( entry, tmp, &pdev->msi_list, list )=0A = {=0A unsigned int i =3D 0, nr =3D 1;=0A- u16 control =3D = 0;=0A- u8 slot =3D PCI_SLOT(pdev->devfn), func =3D PCI_FUNC(pdev->de= vfn);=0A =0A irq =3D entry->irq;=0A desc =3D &irq_desc[irq]= ;=0A@@ -1355,31 +1356,38 @@ int pci_restore_msi_state(struct pci_dev=0A = pdev->seg, pdev->bus, PCI_SLOT(pdev->devfn),=0A = PCI_FUNC(pdev->devfn), i);=0A spin_unlock_irqrestore(= &desc->lock, flags);=0A+ if ( type =3D=3D PCI_CAP_ID_MSIX )=0A+ = pci_conf_write16(pdev->seg, pdev->bus, slot, func,=0A+ = msix_control_reg(pos),=0A+ = control & ~PCI_MSIX_FLAGS_ENABLE);=0A return = -EINVAL;=0A }=0A =0A+ ASSERT(!type || type =3D=3D entry->msi= _attrib.type);=0A+ pos =3D entry->msi_attrib.pos;=0A if ( = entry->msi_attrib.type =3D=3D PCI_CAP_ID_MSI )=0A {=0A = msi_set_enable(pdev, 0);=0A nr =3D entry->msi.nvec;=0A = }=0A- else if ( entry->msi_attrib.type =3D=3D PCI_CAP_ID_MSIX )=0A+ = else if ( !type && entry->msi_attrib.type =3D=3D PCI_CAP_ID_MSIX = )=0A {=0A control =3D pci_conf_read16(pdev->seg, = pdev->bus, slot, func,=0A- msix_contro= l_reg(entry->msi_attrib.pos));=0A+ = msix_control_reg(pos));=0A pci_conf_write16(pdev->seg, = pdev->bus, slot, func,=0A- msix_control_reg(ent= ry->msi_attrib.pos),=0A+ msix_control_reg(pos),= =0A control | (PCI_MSIX_FLAGS_ENABLE |=0A = PCI_MSIX_FLAGS_MASKALL));=0A = if ( unlikely(!memory_decoded(pdev)) )=0A {=0A = spin_unlock_irqrestore(&desc->lock, flags);=0A pci_conf_w= rite16(pdev->seg, pdev->bus, slot, func,=0A- = msix_control_reg(entry->msi_attrib.pos),=0A+ = msix_control_reg(pos),=0A control & = ~PCI_MSIX_FLAGS_ENABLE);=0A return -ENXIO;=0A = }=0A }=0A+ type =3D entry->msi_attrib.type;=0A =0A = msg =3D entry->msg;=0A write_msi_msg(entry, &msg);=0A@@ -1403,9 = +1411,9 @@ int pci_restore_msi_state(struct pci_dev=0A =0A = spin_unlock_irqrestore(&desc->lock, flags);=0A =0A- if ( entry->msi_= attrib.type =3D=3D PCI_CAP_ID_MSI )=0A+ if ( type =3D=3D PCI_CAP_ID_= MSI )=0A {=0A- unsigned int cpos =3D msi_control_reg(ent= ry->msi_attrib.pos);=0A+ unsigned int cpos =3D msi_control_reg(p= os);=0A =0A control =3D pci_conf_read16(pdev->seg, pdev->bus, = slot, func, cpos) &=0A ~PCI_MSI_FLAGS_QSIZE;=0A@@ = -1415,12 +1423,13 @@ int pci_restore_msi_state(struct pci_dev=0A =0A = msi_set_enable(pdev, 1);=0A }=0A- else if ( entry->msi= _attrib.type =3D=3D PCI_CAP_ID_MSIX )=0A- pci_conf_write16(pdev-= >seg, pdev->bus, slot, func,=0A- msix_control_r= eg(entry->msi_attrib.pos),=0A- control | = PCI_MSIX_FLAGS_ENABLE);=0A }=0A =0A+ if ( type =3D=3D PCI_CAP_ID_MSI= X )=0A+ pci_conf_write16(pdev->seg, pdev->bus, slot, func,=0A+ = msix_control_reg(pos),=0A+ = control | PCI_MSIX_FLAGS_ENABLE);=0A+=0A return 0;=0A }=0A =0A --=__Part516581C4.1__= Content-Type: text/plain; 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