From mboxrd@z Thu Jan 1 00:00:00 1970 From: =?windows-1252?Q?Roger_Pau_Monn=E9?= Subject: Re: [PATCH v3 07/32] xen/x86: fix arch_set_info_guest for HVM guests Date: Fri, 24 Jul 2015 13:49:27 +0200 Message-ID: <55B22647.7040301@citrix.com> References: <1435923310-9019-1-git-send-email-roger.pau@citrix.com> <1435923310-9019-8-git-send-email-roger.pau@citrix.com> <55A3E0F102000078000903B5@mail.emea.novell.com> <55B0C100.6000308@citrix.com> <55B0EC520200007800094842@prv-mh.provo.novell.com> <1437651718.19412.92.camel@citrix.com> <55B103DD.4030901@citrix.com> <55B125440200007800094BD2@prv-mh.provo.novell.com> <55B10CDB.5010708@citrix.com> <1437667259.24746.12.camel@citrix.com> <55B11316.2000201@citrix.com> <55B130420200007800094CB8@prv-mh.provo.novell.com> <55B11CBE.8050704@citrix.com> <55B1208C.9090207@citrix.com> <55B211D70200007800094FCF@prv-mh.provo.novell.com> <55B20C9D.5070708@citrix.com> <55B21D47.4010109@citrix.com> Mime-Version: 1.0 Content-Type: text/plain; charset="windows-1252" Content-Transfer-Encoding: quoted-printable Return-path: Received: from mail6.bemta5.messagelabs.com ([195.245.231.135]) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1ZIbTq-0000Ax-1C for xen-devel@lists.xenproject.org; Fri, 24 Jul 2015 11:49:34 +0000 In-Reply-To: <55B21D47.4010109@citrix.com> List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org To: Andrew Cooper , Jan Beulich Cc: xen-devel@lists.xenproject.org, Boris Ostrovsky , Ian Campbell , David Vrabel List-Id: xen-devel@lists.xenproject.org El 24/07/15 a les 13.11, Andrew Cooper ha escrit: > On 24/07/15 10:59, Roger Pau Monn=E9 wrote: >> struct vcpu_hvm_context { >> /* 32bit fields of the structure will be used. */ >> #define _VCPUHVM_MODE_32B 0 >> #define VCPUHVM_MODE_32B (1<<_VCPUHVM_MODE_32B) >> /* 64bit fields of the structure will be used. */ >> #define _VCPUHVM_MODE_64B 1 >> #define VCPUHVM_MODE_64B (1<<_VCPUHVM_MODE_64B) >> #define _VCPUHVM_online 2 >> #define VCPUHVM_online (1<<_VCPUHVM_online ) >> uint32_t flags; /* VCPUHVM_* flags. */ >> struct cpu_hvm_regs user_regs; /* CPU registers. */ >> }; > = > To avoid making the 32bit (and optionally 16bit) massive as a side > effect of 64bit, can I suggest > = > uint32_t flags; > union { > cpu_hvm32_regs; > cpu_hvm64_regs; > }; > = > Which allows hvm32_regs to be a far smaller structure. But what's the benefit of this? vcpu_hvm_context is going to be equally large, and that's what we pass as the hypercall argument. This is mimicking the format of the structure that's already used on ARM, so I would rather keep it as is. >> >> #if defined(__GNUC__) && !defined(__STRICT_ANSI__) >> /* Anonymous union includes both 32- and 64-bit names (e.g., ebp/rbp). */ >> # define __DECL_REG(n64, n32) union { \ >> uint64_t n64; \ >> uint32_t n32; \ >> } >> #else >> /* Non-gcc sources must always use the proper 64-bit name (e.g., rbp). */ >> #define __DECL_REG(n64, n32) uint64_t n64 >> #endif >> >> #define __DECL_GP_REG(n) __DECL_REG(r##n, e##n) >> >> struct cpu_hvm_regs { >> /* General purpose registers. */ >> __DECL_GP_REG(bx); >> __DECL_GP_REG(cx); >> __DECL_GP_REG(dx); >> __DECL_GP_REG(si); >> __DECL_GP_REG(di); >> __DECL_GP_REG(bp); >> __DECL_GP_REG(ax); >> __DECL_GP_REG(ip); >> __DECL_GP_REG(sp); >> __DECL_GP_REG(flags); >> >> /* Control registers. */ >> uint64_t cr[8]; >> /* Valid on amd64 only. */ >> uint64_t efer; >> >> /* Debug registers. */ >> uint64_t db[8]; >> }; >> >> #undef __DECL_GP_REG >> #undef __DECL_REG >> >> Of course the APs will be allowed to start in any mode they wish, >> regardless of the mode the guest is currently running on. > = > To start straight in 64bit, you need gdtr and cs as a minimum > = > With that in mind, room for each of the task registers, and segment > selectors. I was planning to say that on both 32 and 64 bits we start with a flat GDT (like we do for the BSP). But we can also arrange for this to be set by the user. So we would need to add the following fields: uint{16/32/64}_t gdtr; uint16_t ss, es, ds, fs, gs; uint16_t tr; Roger.