From mboxrd@z Thu Jan 1 00:00:00 1970 From: =?windows-1252?Q?Roger_Pau_Monn=E9?= Subject: Re: [PATCH v3 07/32] xen/x86: fix arch_set_info_guest for HVM guests Date: Fri, 24 Jul 2015 17:26:57 +0200 Message-ID: <55B25941.9@citrix.com> References: <1435923310-9019-1-git-send-email-roger.pau@citrix.com> <1435923310-9019-8-git-send-email-roger.pau@citrix.com> <55A3E0F102000078000903B5@mail.emea.novell.com> <55B0C100.6000308@citrix.com> <55B0EC520200007800094842@prv-mh.provo.novell.com> <1437651718.19412.92.camel@citrix.com> <55B103DD.4030901@citrix.com> <55B125440200007800094BD2@prv-mh.provo.novell.com> <55B10CDB.5010708@citrix.com> <1437667259.24746.12.camel@citrix.com> <55B11316.2000201@citrix.com> <55B130420200007800094CB8@prv-mh.provo.novell.com> <55B11CBE.8050704@citrix.com> <55B1208C.9090207@citrix.com> <55B211D70200007800094FCF@prv-mh.provo.novell.com> <55B20C9D.5070708@citrix.com> <55B233890200007800095124@prv-mh.provo.novell.com> <55B22B5A.8020304@citrix.com> <55B24F4A02000078000952CC@prv-mh.provo.novell.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mail6.bemta3.messagelabs.com ([195.245.230.39]) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1ZIesn-0007YL-Sv for xen-devel@lists.xenproject.org; Fri, 24 Jul 2015 15:27:34 +0000 In-Reply-To: <55B24F4A02000078000952CC@prv-mh.provo.novell.com> List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org To: Jan Beulich Cc: Ian Campbell , Andrew Cooper , David Vrabel , xen-devel@lists.xenproject.org, Boris Ostrovsky List-Id: xen-devel@lists.xenproject.org El 24/07/15 a les 14.44, Jan Beulich ha escrit: >>>> On 24.07.15 at 14:11, wrote: >> It seems kind of pointless IMHO, the reason to have the union is to be >> able to access the registers using the native nomenclature, but if a >> register doesn't exist in a specific bitness I don't see the point of >> adding such "invalid" names. > > No - put side by side an item valid in only a subset modes and an > item only valid outside of that subset. OK, let me see if I got that right. >> Or your idea was to put all the bitness specific registers inside of >> another separate structure and then unionize them? AFAICT the 16 and >> 32bit structures are going to be empty. > > How that? 64-bit mode e.g. doesn't need full descriptor data for > many of the segment registers. Please bear with me, but AFAIK cs, ds, es and ss still need to point to a GDT entry with a 0 base and a limit of 2^64. What about the following layout: #if defined(__GNUC__) && !defined(__STRICT_ANSI__) /* Anonymous union includes 16-, 32- and 64-bit names (e.g., bp/ebp/rbp). */ # define __DECL_REG(n64, n32, n16) union { \ uint64_t n64; \ uint32_t n32; \ uint16_t n16; \ } #else /* Non-gcc sources must always use the proper 64-bit name (e.g., rbp). */ #define __DECL_REG(n64, n32, n16) uint64_t n64 #endif #define __DECL_GP_REG(n) __DECL_REG(r##n, e##n, n) struct cpu_x86_16 { /* Control registers. */ uint32_t cr[8]; /* Debug registers. */ uint32_t dr[8]; /* GDT descriptor address. */ uint16_t gdtr; }; struct cpu_x86_32 { /* Control registers. */ uint32_t cr[8]; /* Debug registers. */ uint32_t dr[8]; /* GDT descriptor address. */ uint32_t gdtr; }; struct cpu_x86_64 { /* Additional amd64 general purpose registers. */ uint64_t r8, r9, r10, r11, r12, r13, r14, r15; /* Control registers. */ uint64_t cr[9]; /* Debug registers. */ uint64_t dr[8]; /* Extended Feature Enable Register. */ uint64_t efer; /* GDT descriptor address. */ uint64_t gdtr; }; struct cpu_hvm_regs { /* General purpose registers. */ __DECL_GP_REG(ax); __DECL_GP_REG(bx); __DECL_GP_REG(cx); __DECL_GP_REG(dx); /* Index registers. */ __DECL_GP_REG(di); __DECL_GP_REG(si); /* Pointer registers. */ __DECL_GP_REG(bp); __DECL_GP_REG(sp); /* Instruction pointer. */ __DECL_GP_REG(ip); /* Status register. */ __DECL_GP_REG(flags); /* Segment registers. */ uint16_t cs; uint16_t ds; uint16_t es; uint16_t ss; uint16_t fs; uint16_t gs; /* Task state segment. */ uint16_t ts; /* Bitness specific registers. */ union { struct cpu_x86_16 x86_16; struct cpu_x86_32 x86_32; struct cpu_x86_64 x86_64; }; }; struct vcpu_hvm_context { /* 16bit fields of the strucutre will be used. */ #define _VCPUHVM_MODE_16B 0 #define VCPUHVM_MODE_16B (1<<_VCPUHVM_MODE_16B) /* 32bit fields of the structure will be used. */ #define _VCPUHVM_MODE_32B 1 #define VCPUHVM_MODE_32B (1<<_VCPUHVM_MODE_32B) /* 64bit fields of the structure will be used. */ #define _VCPUHVM_MODE_64B 2 #define VCPUHVM_MODE_64B (1<<_VCPUHVM_MODE_64B) uint32_t flags; /* VCPUHVM_* flags. */ struct cpu_hvm_regs user_regs; /* CPU registers. */ }; #undef __DECL_GP_REG #undef __DECL_REG