From: David Vrabel <david.vrabel@citrix.com>
To: Jan Beulich <JBeulich@suse.com>, David Vrabel <david.vrabel@citrix.com>
Cc: Kevin Tian <kevin.tian@intel.com>,
Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>,
Andrew Cooper <andrew.cooper3@citrix.com>,
Donald D Dugger <donald.d.dugger@intel.com>,
Aravind Gopalakrishnan <aravind.gopalakrishnan@amd.com>,
Jun Nakajima <jun.nakajima@intel.com>,
Sherry Hurwitz <sherry.hurwitz@amd.com>,
xen-devel@lists.xenproject.org
Subject: Re: [PATCHv2 1/3] x86/fpu: improve check for XSAVE* not writing FIP/FDP fields
Date: Tue, 23 Feb 2016 17:42:19 +0000 [thread overview]
Message-ID: <56CC99FB.9010805@citrix.com> (raw)
In-Reply-To: <56CC81CC02000078000D5431@prv-mh.provo.novell.com>
On 23/02/16 14:59, Jan Beulich wrote:
>>>> On 23.02.16 at 12:05, <david.vrabel@citrix.com> wrote:
>> --- a/xen/arch/x86/xstate.c
>> +++ b/xen/arch/x86/xstate.c
>> @@ -263,41 +263,24 @@ void xsave(struct vcpu *v, uint64_t mask)
>>
>> if ( word_size <= 0 || !is_pv_32bit_vcpu(v) )
>> {
>> - typeof(ptr->fpu_sse.fip.sel) fcs = ptr->fpu_sse.fip.sel;
>> - typeof(ptr->fpu_sse.fdp.sel) fds = ptr->fpu_sse.fdp.sel;
>> + uint64_t bad_fip;
>>
>> - if ( cpu_has_xsaveopt || cpu_has_xsaves )
>> - {
>> - /*
>> - * XSAVEOPT/XSAVES may not write the FPU portion even when the
>> - * respective mask bit is set. For the check further down to work
>> - * we hence need to put the save image back into the state that
>> - * it was in right after the previous XSAVEOPT.
>> - */
>> - if ( word_size > 0 &&
>> - (ptr->fpu_sse.x[FPU_WORD_SIZE_OFFSET] == 4 ||
>> - ptr->fpu_sse.x[FPU_WORD_SIZE_OFFSET] == 2) )
>> - {
>> - ptr->fpu_sse.fip.sel = 0;
>> - ptr->fpu_sse.fdp.sel = 0;
>> - }
>> - }
>> + /*
>> + * FIP/FDP may not be written in some cases (e.g., if
>> + * XSAVEOPT/XSAVES is used, or on AMD CPUs if an exception
>> + * isn't pending).
>> + *
>> + * To tell if the hardware writes these fields, make the FIP
>> + * field non-canonical by flipping the top bit.
>> + */
>> + bad_fip = ptr->fpu_sse.fip.addr ^= 1ull << 63;
>>
>> XSAVE("0x48,");
>>
>> - if ( !(mask & ptr->xsave_hdr.xstate_bv & XSTATE_FP) ||
>> - /*
>> - * AMD CPUs don't save/restore FDP/FIP/FOP unless an exception
>> - * is pending.
>> - */
>> - (!(ptr->fpu_sse.fsw & 0x0080) &&
>> - boot_cpu_data.x86_vendor == X86_VENDOR_AMD) )
>> + /* FIP/FDP not updated? Restore the old FIP value. */
>> + if ( ptr->fpu_sse.fip.addr == bad_fip )
>> {
>> - if ( (cpu_has_xsaveopt || cpu_has_xsaves) && word_size > 0 )
>> - {
>> - ptr->fpu_sse.fip.sel = fcs;
>> - ptr->fpu_sse.fdp.sel = fds;
>> - }
>> + ptr->fpu_sse.fip.addr ^= 1ull << 63;
>> return;
>> }
>
> While indeed this is a lot more simple, it puts us on thin ice,
> utilizing undocumented behavior: You make us depend on FIP
> actually being a 48-bit register which gets sign-extended to 64
> bits upon saving, and truncated during restore. While all CPUs
> I've tested so far match this requirement, Intel ones (other
> than AMD's) do not match this in behavior for FDP. Since this
> already makes clear that AMD's are buggy (losing relevant
> state, since FPU operations using FS: or GS: may use non-
> canonical virtual addresses, becoming canonical once
> converted to linear ones) and hence need fixing, it would
> remain to be seen whether they wouldn't at once extend both
> FDP and FIP to 64 bits.
I'm not sure what you're concerned about:
a) Executing a FP instruction might load FIP with a non-canonical RIP?
b) All 2^64 addresses might be canonical if the valid virtual address is
64-bits wide?
c) A guest might load arbitrary data into a 64-bit wide FIP register
(which may look like a non-canonical address)?
But whatever, I'll drop this patch.
(I would hope that new AMD processors go down the Intel route and remove
the FCS/FDS registers.)
David
next prev parent reply other threads:[~2016-02-23 17:42 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-02-23 11:05 [PATCHv2 0/3] x86: workaround inability to fully restore FPU state David Vrabel
2016-02-23 11:05 ` [PATCHv2 1/3] x86/fpu: improve check for XSAVE* not writing FIP/FDP fields David Vrabel
2016-02-23 11:18 ` Andrew Cooper
2016-02-23 11:54 ` David Vrabel
2016-02-23 14:07 ` Jan Beulich
2016-02-23 14:59 ` Jan Beulich
2016-02-23 17:42 ` David Vrabel [this message]
2016-02-24 7:51 ` Jan Beulich
2016-02-24 10:37 ` Tian, Kevin
2016-02-24 10:49 ` Jan Beulich
2016-03-18 18:23 ` Lai, Paul C
2016-02-23 11:05 ` [PATCHv2 2/3] x86/fpu: Add a per-domain field to set the width of FIP/FDP David Vrabel
2016-02-23 11:10 ` Andrew Cooper
2016-02-23 11:53 ` David Vrabel
2016-02-23 15:24 ` Jan Beulich
2016-02-23 16:27 ` David Vrabel
2016-02-23 16:39 ` Jan Beulich
2016-02-23 11:05 ` [PATCHv2 3/3] x86/hvm: add HVM_PARAM_X87_FIP_WIDTH David Vrabel
2016-02-23 11:20 ` Andrew Cooper
2016-02-24 11:51 ` Wei Liu
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=56CC99FB.9010805@citrix.com \
--to=david.vrabel@citrix.com \
--cc=JBeulich@suse.com \
--cc=andrew.cooper3@citrix.com \
--cc=aravind.gopalakrishnan@amd.com \
--cc=donald.d.dugger@intel.com \
--cc=jun.nakajima@intel.com \
--cc=kevin.tian@intel.com \
--cc=sherry.hurwitz@amd.com \
--cc=suravee.suthikulpanit@amd.com \
--cc=xen-devel@lists.xenproject.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).