From mboxrd@z Thu Jan 1 00:00:00 1970 From: "Jan Beulich" Subject: [PATCH 1/3] x86: rename XMM* features to SSE* Date: Fri, 11 Mar 2016 10:33:44 -0700 Message-ID: <56E30F8802000078000DBB8B@prv-mh.provo.novell.com> References: <56E30EA102000078000DBB7F@prv-mh.provo.novell.com> Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="=__PartB4830C68.1__=" Return-path: Received: from mail6.bemta3.messagelabs.com ([195.245.230.39]) by lists.xen.org with esmtp (Exim 4.84) (envelope-from ) id 1aeQwd-0004A4-Lt for xen-devel@lists.xenproject.org; Fri, 11 Mar 2016 17:33:47 +0000 In-Reply-To: <56E30EA102000078000DBB7F@prv-mh.provo.novell.com> List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" To: xen-devel Cc: Andrew Cooper , Keir Fraser List-Id: xen-devel@lists.xenproject.org This is a MIME message. If you are reading this text, you may want to consider changing to a mail reader or gateway that understands how to properly handle MIME multipart messages. --=__PartB4830C68.1__= Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: quoted-printable Content-Disposition: inline The latter are their canonical names, used already in the instruction emulator. Signed-off-by: Jan Beulich Reviewed-by: Andrew Cooper --- a/xen/arch/x86/cpu/common.c +++ b/xen/arch/x86/cpu/common.c @@ -205,12 +205,12 @@ static void __init early_cpu_detect(void c->x86_model +=3D ((eax >> 16) & 0xF) << 4; c->x86_mask =3D eax & 15; edx &=3D ~cleared_caps[cpufeat_word(X86_FEATURE_FPU)]; - ecx &=3D ~cleared_caps[cpufeat_word(X86_FEATURE_XMM3)]; + ecx &=3D ~cleared_caps[cpufeat_word(X86_FEATURE_SSE3)]; if (edx & cpufeat_mask(X86_FEATURE_CLFLUSH)) c->x86_cache_alignment =3D ((ebx >> 8) & 0xff) * 8; /* Leaf 0x1 capabilities filled in early for Xen. */ c->x86_capability[cpufeat_word(X86_FEATURE_FPU)] =3D edx; - c->x86_capability[cpufeat_word(X86_FEATURE_XMM3)] =3D ecx; + c->x86_capability[cpufeat_word(X86_FEATURE_SSE3)] =3D ecx; =20 if ( cpuid_eax(0x80000000) >=3D 0x80000008 ) paddr_bits =3D cpuid_eax(0x80000008) & 0xff; @@ -249,7 +249,7 @@ static void generic_identify(struct cpui c->cpuid_level =3D cpuid_eax(0); cpuid(0x00000001, &eax, &ebx, &ecx, &edx); c->x86_capability[cpufeat_word(X86_FEATURE_FPU)] =3D edx; - c->x86_capability[cpufeat_word(X86_FEATURE_XMM3)] =3D ecx; + c->x86_capability[cpufeat_word(X86_FEATURE_SSE3)] =3D ecx; =20 if ( cpu_has(c, X86_FEATURE_CLFLUSH) ) c->x86_clflush_size =3D ((ebx >> 8) & 0xff) * 8; --- a/xen/arch/x86/hvm/hvm.c +++ b/xen/arch/x86/hvm/hvm.c @@ -2029,7 +2029,7 @@ unsigned long hvm_cr4_guest_reserved_bit X86_CR4_PCE | (leaf1_edx & cpufeat_mask(X86_FEATURE_FXSR) ? X86_CR4_OSFXSR : 0) | - (leaf1_edx & cpufeat_mask(X86_FEATURE_XMM) ? + (leaf1_edx & cpufeat_mask(X86_FEATURE_SSE) ? X86_CR4_OSXMMEXCPT : 0) | ((restore || nestedhvm_enabled(v->domain)) && (leaf1_ecx & cpufeat_mask(X86_FEATURE_VMXE)) ? --- a/xen/arch/x86/hvm/vmx/vvmx.c +++ b/xen/arch/x86/hvm/vmx/vvmx.c @@ -1963,7 +1963,7 @@ int nvmx_msr_read_intercept(unsigned int data |=3D X86_CR4_PGE; if ( edx & cpufeat_mask(X86_FEATURE_FXSR) ) data |=3D X86_CR4_OSFXSR; - if ( edx & cpufeat_mask(X86_FEATURE_XMM) ) + if ( edx & cpufeat_mask(X86_FEATURE_SSE) ) data |=3D X86_CR4_OSXMMEXCPT; if ( ecx & cpufeat_mask(X86_FEATURE_VMXE) ) data |=3D X86_CR4_VMXE; --- a/xen/include/asm-x86/amd.h +++ b/xen/include/asm-x86/amd.h @@ -22,7 +22,7 @@ cpufeat_mask(X86_FEATURE_CMOV) | cpufeat_mask(X86_FEATURE_PAT) = | \ cpufeat_mask(X86_FEATURE_PSE36) | cpufeat_mask(X86_FEATURE_CLFLUSH)= | \ cpufeat_mask(X86_FEATURE_MMX) | cpufeat_mask(X86_FEATURE_FXSR) = | \ - cpufeat_mask(X86_FEATURE_XMM) | cpufeat_mask(X86_FEATURE_XMM2)) + cpufeat_mask(X86_FEATURE_SSE) | cpufeat_mask(X86_FEATURE_SSE2)) #define AMD_EXTFEATURES_K8_REV_C_ECX 0 #define AMD_EXTFEATURES_K8_REV_C_EDX ( = \ cpufeat_mask(X86_FEATURE_FPU) | cpufeat_mask(X86_FEATURE_VME) = | \ @@ -48,7 +48,7 @@ =20 /* Family 0Fh, Revision E */ #define AMD_FEATURES_K8_REV_E_ECX (AMD_FEATURES_K8_REV_D_ECX | \ - cpufeat_mask(X86_FEATURE_XMM3)) + cpufeat_mask(X86_FEATURE_SSE3)) #define AMD_FEATURES_K8_REV_E_EDX (AMD_FEATURES_K8_REV_D_EDX | \ cpufeat_mask(X86_FEATURE_HT)) #define AMD_EXTFEATURES_K8_REV_E_ECX (AMD_EXTFEATURES_K8_REV_D_ECX |\ --- a/xen/include/asm-x86/cpufeature.h +++ b/xen/include/asm-x86/cpufeature.h @@ -38,8 +38,8 @@ #define X86_FEATURE_MMX (0*32+23) /* Multimedia Extensions = */ #define X86_FEATURE_FXSR (0*32+24) /* FXSAVE and FXRSTOR instruction= s (fast save and restore */ /* of FPU context), and = CR4.OSFXSR available */ -#define X86_FEATURE_XMM (0*32+25) /* Streaming SIMD = Extensions */ -#define X86_FEATURE_XMM2 (0*32+26) /* Streaming SIMD Extensions-2 = */ +#define X86_FEATURE_SSE (0*32+25) /* Streaming SIMD = Extensions */ +#define X86_FEATURE_SSE2 (0*32+26) /* Streaming SIMD Extensions-2 = */ #define X86_FEATURE_SELFSNOOP (0*32+27) /* CPU self snoop */ #define X86_FEATURE_HT (0*32+28) /* Hyper-Threading */ #define X86_FEATURE_ACC (0*32+29) /* Automatic clock = control */ @@ -78,7 +78,7 @@ #define X86_FEATURE_APERFMPERF (3*32+16) /* APERFMPERF */ =20 /* Intel-defined CPU features, CPUID level 0x00000001 (ecx), word 4 */ -#define X86_FEATURE_XMM3 (4*32+ 0) /* Streaming SIMD Extensions-3 = */ +#define X86_FEATURE_SSE3 (4*32+ 0) /* Streaming SIMD Extensions-3 = */ #define X86_FEATURE_PCLMULQDQ (4*32+ 1) /* Carry-less mulitplication */ #define X86_FEATURE_DTES64 (4*32+ 2) /* 64-bit Debug Store */ #define X86_FEATURE_MWAIT (4*32+ 3) /* Monitor/Mwait support */ @@ -183,7 +183,9 @@ #define cpu_has_sep boot_cpu_has(X86_FEATURE_SEP) #define cpu_has_mtrr 1 #define cpu_has_mmx 1 -#define cpu_has_xmm3 boot_cpu_has(X86_FEATURE_XMM3) +#define cpu_has_sse boot_cpu_has(X86_FEATURE_SSE) +#define cpu_has_sse2 boot_cpu_has(X86_FEATURE_SSE2) +#define cpu_has_sse3 boot_cpu_has(X86_FEATURE_SSE3) #define cpu_has_ht boot_cpu_has(X86_FEATURE_HT) #define cpu_has_mp 1 #define cpu_has_nx boot_cpu_has(X86_FEATURE_NX) --=__PartB4830C68.1__= Content-Type: text/plain; name="x86-feature-xmmN-sseN.patch" Content-Transfer-Encoding: quoted-printable Content-Disposition: attachment; filename="x86-feature-xmmN-sseN.patch" x86: rename XMM* features to SSE*=0A=0AThe latter are their canonical = names, used already in the instruction=0Aemulator.=0A=0ASigned-off-by: Jan = Beulich =0AReviewed-by: Andrew Cooper =0A=0A--- a/xen/arch/x86/cpu/common.c=0A+++ b/xen/arch/x86/cpu/com= mon.c=0A@@ -205,12 +205,12 @@ static void __init early_cpu_detect(void=0A = c->x86_model +=3D ((eax >> 16) & 0xF) << 4;=0A c->x86_mask =3D = eax & 15;=0A edx &=3D ~cleared_caps[cpufeat_word(X86_FEATURE_FPU)];=0A- = ecx &=3D ~cleared_caps[cpufeat_word(X86_FEATURE_XMM3)];=0A+ ecx &=3D = ~cleared_caps[cpufeat_word(X86_FEATURE_SSE3)];=0A if (edx & = cpufeat_mask(X86_FEATURE_CLFLUSH))=0A c->x86_cache_alignment =3D = ((ebx >> 8) & 0xff) * 8;=0A /* Leaf 0x1 capabilities filled in early = for Xen. */=0A c->x86_capability[cpufeat_word(X86_FEATURE_FPU)] =3D = edx;=0A- c->x86_capability[cpufeat_word(X86_FEATURE_XMM3)] =3D = ecx;=0A+ c->x86_capability[cpufeat_word(X86_FEATURE_SSE3)] =3D = ecx;=0A =0A if ( cpuid_eax(0x80000000) >=3D 0x80000008 )=0A = paddr_bits =3D cpuid_eax(0x80000008) & 0xff;=0A@@ -249,7 +249,7 @@ static = void generic_identify(struct cpui=0A c->cpuid_level =3D cpuid_eax(0);=0A= cpuid(0x00000001, &eax, &ebx, &ecx, &edx);=0A c->x86_capability[c= pufeat_word(X86_FEATURE_FPU)] =3D edx;=0A- c->x86_capability[cpufeat_w= ord(X86_FEATURE_XMM3)] =3D ecx;=0A+ c->x86_capability[cpufeat_word(X86_= FEATURE_SSE3)] =3D ecx;=0A =0A if ( cpu_has(c, X86_FEATURE_CLFLUSH) )=0A = c->x86_clflush_size =3D ((ebx >> 8) & 0xff) * 8;=0A--- a/xen/arch/x= 86/hvm/hvm.c=0A+++ b/xen/arch/x86/hvm/hvm.c=0A@@ -2029,7 +2029,7 @@ = unsigned long hvm_cr4_guest_reserved_bit=0A X86_CR4_PCE |=0A = (leaf1_edx & cpufeat_mask(X86_FEATURE_FXSR) ?=0A = X86_CR4_OSFXSR : 0) |=0A- (leaf1_edx & cpufeat_mask(X86_FEATURE= _XMM) ?=0A+ (leaf1_edx & cpufeat_mask(X86_FEATURE_SSE) ?=0A = X86_CR4_OSXMMEXCPT : 0) |=0A ((restore || = nestedhvm_enabled(v->domain)) &&=0A (leaf1_ecx & cpufeat_mask= (X86_FEATURE_VMXE)) ?=0A--- a/xen/arch/x86/hvm/vmx/vvmx.c=0A+++ b/xen/arch/= x86/hvm/vmx/vvmx.c=0A@@ -1963,7 +1963,7 @@ int nvmx_msr_read_intercept(unsi= gned int=0A data |=3D X86_CR4_PGE;=0A if ( edx & = cpufeat_mask(X86_FEATURE_FXSR) )=0A data |=3D X86_CR4_OSFXSR;= =0A- if ( edx & cpufeat_mask(X86_FEATURE_XMM) )=0A+ if ( edx = & cpufeat_mask(X86_FEATURE_SSE) )=0A data |=3D X86_CR4_OSXMMEXC= PT;=0A if ( ecx & cpufeat_mask(X86_FEATURE_VMXE) )=0A = data |=3D X86_CR4_VMXE;=0A--- a/xen/include/asm-x86/amd.h=0A+++ b/xen/inclu= de/asm-x86/amd.h=0A@@ -22,7 +22,7 @@=0A cpufeat_mask(X86_FEATURE_CM= OV) | cpufeat_mask(X86_FEATURE_PAT) | \=0A cpufeat_mask(X86_FEATURE_PS= E36) | cpufeat_mask(X86_FEATURE_CLFLUSH)| \=0A cpufeat_mask(X86_FEATURE_MM= X) | cpufeat_mask(X86_FEATURE_FXSR) | \=0A- cpufeat_mask(X86_FEATURE_XM= M) | cpufeat_mask(X86_FEATURE_XMM2))=0A+ cpufeat_mask(X86_FEATURE_SS= E) | cpufeat_mask(X86_FEATURE_SSE2))=0A #define AMD_EXTFEATURES_K8_REV_C_= ECX 0=0A #define AMD_EXTFEATURES_K8_REV_C_EDX ( = \=0A cpufeat_mask(X86_FEATURE_FPU) | cpufeat_mask(X= 86_FEATURE_VME) | \=0A@@ -48,7 +48,7 @@=0A =0A /* Family 0Fh, Revision E = */=0A #define AMD_FEATURES_K8_REV_E_ECX (AMD_FEATURES_K8_REV_D_ECX = | \=0A- cpufeat_mask(X86_FEATURE_XMM3))=0A+ cpufeat_mask(X86_FE= ATURE_SSE3))=0A #define AMD_FEATURES_K8_REV_E_EDX (AMD_FEATURES_K8_R= EV_D_EDX | \=0A cpufeat_mask(X86_FEATURE_HT))=0A #define AMD_EXTFEA= TURES_K8_REV_E_ECX (AMD_EXTFEATURES_K8_REV_D_ECX |\=0A--- a/xen/include= /asm-x86/cpufeature.h=0A+++ b/xen/include/asm-x86/cpufeature.h=0A@@ -38,8 = +38,8 @@=0A #define X86_FEATURE_MMX (0*32+23) /* Multimedia = Extensions */=0A #define X86_FEATURE_FXSR (0*32+24) /* FXSAVE and = FXRSTOR instructions (fast save and restore */=0A = /* of FPU context), and CR4.OSFXSR available */=0A-#define = X86_FEATURE_XMM (0*32+25) /* Streaming SIMD Extensions */=0A-#defin= e X86_FEATURE_XMM2 (0*32+26) /* Streaming SIMD Extensions-2 */=0A+#def= ine X86_FEATURE_SSE (0*32+25) /* Streaming SIMD Extensions = */=0A+#define X86_FEATURE_SSE2 (0*32+26) /* Streaming SIMD Extensions-2 = */=0A #define X86_FEATURE_SELFSNOOP (0*32+27) /* CPU self snoop */=0A = #define X86_FEATURE_HT (0*32+28) /* Hyper-Threading */=0A #define = X86_FEATURE_ACC (0*32+29) /* Automatic clock control */=0A@@ -78,7 = +78,7 @@=0A #define X86_FEATURE_APERFMPERF (3*32+16) /* APERFMPERF */=0A = =0A /* Intel-defined CPU features, CPUID level 0x00000001 (ecx), word 4 = */=0A-#define X86_FEATURE_XMM3 (4*32+ 0) /* Streaming SIMD Extensions-3 = */=0A+#define X86_FEATURE_SSE3 (4*32+ 0) /* Streaming SIMD Extensions-3 = */=0A #define X86_FEATURE_PCLMULQDQ (4*32+ 1) /* Carry-less mulitplicat= ion */=0A #define X86_FEATURE_DTES64 (4*32+ 2) /* 64-bit Debug Store = */=0A #define X86_FEATURE_MWAIT (4*32+ 3) /* Monitor/Mwait support */=0A@@ = -183,7 +183,9 @@=0A #define cpu_has_sep boot_cpu_has(X86_FEATURE_SE= P)=0A #define cpu_has_mtrr 1=0A #define cpu_has_mmx = 1=0A-#define cpu_has_xmm3 boot_cpu_has(X86_FEATURE_XMM3)=0A+#= define cpu_has_sse boot_cpu_has(X86_FEATURE_SSE)=0A+#define = cpu_has_sse2 boot_cpu_has(X86_FEATURE_SSE2)=0A+#define = cpu_has_sse3 boot_cpu_has(X86_FEATURE_SSE3)=0A #define = cpu_has_ht boot_cpu_has(X86_FEATURE_HT)=0A #define cpu_has_mp = 1=0A #define cpu_has_nx boot_cpu_has(X86_FEATURE_NX)=0A --=__PartB4830C68.1__= Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: base64 Content-Disposition: inline X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX18KWGVuLWRldmVs IG1haWxpbmcgbGlzdApYZW4tZGV2ZWxAbGlzdHMueGVuLm9yZwpodHRwOi8vbGlzdHMueGVuLm9y Zy94ZW4tZGV2ZWwK --=__PartB4830C68.1__=--