From: Julien Grall <julien.grall@arm.com>
To: Shanker Donthineni <shankerd@codeaurora.org>,
Stefano Stabellini <stefano.stabellini@eu.citrix.com>,
xen-devel@lists.xensource.com
Cc: Philip Elcan <pelcan@codeaurora.org>,
Ian Campbell <ian.campbell@citrix.com>,
Vikram Sethi <vikrams@codeaurora.org>
Subject: Re: [PATCH] xen/arm64: Fix incorrect memory region size in TCR2_EL2
Date: Mon, 14 Mar 2016 14:58:06 +0000 [thread overview]
Message-ID: <56E6D17E.40402@arm.com> (raw)
In-Reply-To: <56E6CC9B.40108@codeaurora.org>
On 14/03/16 14:37, Shanker Donthineni wrote:
> HI Jullen,
Hi Shanker,
> On 03/12/2016 07:13 AM, Julien Grall wrote:
>> Hi Shanker,
>>
>> On 11/03/2016 04:28, Shanker Donthineni wrote:
>>> The maximum and minimum values for T0SZ depend on level of
>>> translation as per AArch64 Virtual Memory System Architecture.
>>> The current code sets T0SZ to zero in TCR2_EL2 which is not
>>
>> s/TCR2_EL2/TCR_EL2/
>>
>
> Sorry for typo, I will fix in next patch
>
>>> valid and also might see unexpected behavior on some CPUs.
>>
>> Can you provide more details?
>>
>
> We are not able to boot XEN on Qualcomm platforms and CPU hung after
> after executing this line of ASM code.
>
>> I looked at the specification, programming the field T0SZ to 0 is valid
>> (see D4-1463 ARM DDI 0487A.b):
>>
>> "For a stage 1 translation
>> The minimum TxSZ value is 16. If TxSZ is programmed to a value smaller
>> than 16 then the implementation behaves as if the field were programmed
>> to 16 for all purposes other than reading back the value of the field."
>>
>
> The behavior of T0SZ=0 is described in ARM spec (DDI0487A_h, page 1752). Still I think setting
> the T0SZ to 48bit is the right fix similar to LINUX KVM64 EL2 code.
>
> For a stage 1 translation
> The minimum TxSZ value is 16. If TxSZ is programmed to a value smaller than 16 then it is
> IMPLEMENTATION DEFINED whether:
>
> • The implementation behaves as if the field were programmed to 16 for all purposes other than
> reading back the value of the field.
>
> • Any use of the TxSZ value generates a stage 1 Level 0 Translation fault.
Sorry, I was looking at an older version of the ARM ARM where only a
single possible behavior was described. So this change looks valid to me.
Can you please mention the version and the section of the spec in the
commit message?
Regards,
--
Julien Grall
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prev parent reply other threads:[~2016-03-14 14:58 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-03-10 21:28 [PATCH] xen/arm64: Fix incorrect memory region size in TCR2_EL2 Shanker Donthineni
2016-03-12 13:13 ` Julien Grall
2016-03-14 14:37 ` Shanker Donthineni
2016-03-14 14:58 ` Julien Grall [this message]
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