From mboxrd@z Thu Jan 1 00:00:00 1970 From: "Jan Beulich" Subject: [PATCH] libxc/x86: XSAVE related adjustments Date: Tue, 22 Mar 2016 07:05:55 -0600 Message-ID: <56F1514302000078000DF2CD@prv-mh.provo.novell.com> Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="=__PartAF980523.2__=" Return-path: Received: from mail6.bemta14.messagelabs.com ([193.109.254.103]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1aiM0W-00060i-DU for xen-devel@lists.xenproject.org; Tue, 22 Mar 2016 13:06:00 +0000 List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" To: xen-devel Cc: Andrew Cooper , Wei Liu , Ian Jackson , Stefano Stabellini List-Id: xen-devel@lists.xenproject.org This is a MIME message. If you are reading this text, you may want to consider changing to a mail reader or gateway that understands how to properly handle MIME multipart messages. --=__PartAF980523.2__= Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: quoted-printable Content-Disposition: inline - don't unintentionally increase features reported by sub-leaf 0 EDX:EAX - don't discard the known flags in sub-leaves 2..63 ECX - handle components 32...62 (EDX) in sub-leaf 1 consistently with 0...31 (ECX) - zap sub-leaves beyond 62 Signed-off-by: Jan Beulich --- While obviously requiring re-basing on either end when taking Andrew's CPUID levelling series into account, the changes done here appear to be orthogonal to those done in his series. --- a/tools/libxc/xc_cpuid_x86.c +++ b/tools/libxc/xc_cpuid_x86.c @@ -281,10 +281,14 @@ static void intel_xc_cpuid_policy(xc_int } } =20 +/* Leaf 1, EAX: */ #define XSAVEOPT (1 << 0) #define XSAVEC (1 << 1) #define XGETBV1 (1 << 2) #define XSAVES (1 << 3) +/* Leaves beyond 1, ECX: */ +#define XSTATE_XSS (1 << 0) +#define XSTATE_ALIGN64 (1 << 1) /* Configure extended state enumeration leaves (0x0000000D for xsave) */ static void xc_cpuid_config_xsave(xc_interface *xch, const struct cpuid_domain_info *info, @@ -300,9 +304,9 @@ static void xc_cpuid_config_xsave(xc_int { case 0:=20 /* EAX: low 32bits of xfeature_enabled_mask */ - regs[0] =3D info->xfeature_mask & 0xFFFFFFFF; + regs[0] &=3D info->xfeature_mask; /* EDX: high 32bits of xfeature_enabled_mask */ - regs[3] =3D (info->xfeature_mask >> 32) & 0xFFFFFFFF; + regs[3] &=3D info->xfeature_mask >> 32; /* ECX: max size required by all HW features */ { unsigned int _input[2] =3D {0xd, 0x0}, _regs[4]; @@ -325,16 +329,20 @@ static void xc_cpuid_config_xsave(xc_int if ( !info->hvm ) regs[0] &=3D ~XSAVES; regs[2] &=3D info->xfeature_mask; - regs[3] =3D 0; + regs[3] &=3D info->xfeature_mask >> 32; break; - case 2 ... 63: /* sub-leaves */ + case 2 ... 62: /* per-component sub-leaves */ if ( !(info->xfeature_mask & (1ULL << input[1])) ) { regs[0] =3D regs[1] =3D regs[2] =3D regs[3] =3D 0; break; } /* Don't touch EAX, EBX. Also cleanup ECX and EDX */ - regs[2] =3D regs[3] =3D 0; + regs[2] &=3D XSTATE_XSS | XSTATE_ALIGN64; + regs[3] =3D 0; + break; + default: + regs[0] =3D regs[1] =3D regs[2] =3D regs[3] =3D 0; break; } } --=__PartAF980523.2__= Content-Type: text/plain; name="libxc-x86-cpuid-xstate.patch" Content-Transfer-Encoding: quoted-printable Content-Disposition: attachment; filename="libxc-x86-cpuid-xstate.patch" libxc/x86: XSAVE related adjustments=0A=0A- don't unintentionally increase = features reported by sub-leaf 0=0A EDX:EAX=0A- don't discard the known = flags in sub-leaves 2..63 ECX=0A- handle components 32...62 (EDX) in = sub-leaf 1 consistently with=0A 0...31 (ECX)=0A- zap sub-leaves beyond = 62=0A=0ASigned-off-by: Jan Beulich =0A---=0AWhile = obviously requiring re-basing on either end when taking Andrew's=0ACPUID = levelling series into account, the changes done here appear to=0Abe = orthogonal to those done in his series.=0A=0A--- a/tools/libxc/xc_cpuid_x86= .c=0A+++ b/tools/libxc/xc_cpuid_x86.c=0A@@ -281,10 +281,14 @@ static void = intel_xc_cpuid_policy(xc_int=0A }=0A }=0A =0A+/* Leaf 1, EAX: */=0A = #define XSAVEOPT (1 << 0)=0A #define XSAVEC (1 << 1)=0A = #define XGETBV1 (1 << 2)=0A #define XSAVES (1 << 3)=0A+/* = Leaves beyond 1, ECX: */=0A+#define XSTATE_XSS (1 << 0)=0A+#define = XSTATE_ALIGN64 (1 << 1)=0A /* Configure extended state enumeration leaves = (0x0000000D for xsave) */=0A static void xc_cpuid_config_xsave(xc_interface= *xch,=0A const struct cpuid_domain_info = *info,=0A@@ -300,9 +304,9 @@ static void xc_cpuid_config_xsave(xc_int=0A = {=0A case 0: =0A /* EAX: low 32bits of xfeature_enabled_mask = */=0A- regs[0] =3D info->xfeature_mask & 0xFFFFFFFF;=0A+ = regs[0] &=3D info->xfeature_mask;=0A /* EDX: high 32bits of = xfeature_enabled_mask */=0A- regs[3] =3D (info->xfeature_mask >> = 32) & 0xFFFFFFFF;=0A+ regs[3] &=3D info->xfeature_mask >> 32;=0A = /* ECX: max size required by all HW features */=0A {=0A = unsigned int _input[2] =3D {0xd, 0x0}, _regs[4];=0A@@ -325,16 = +329,20 @@ static void xc_cpuid_config_xsave(xc_int=0A if ( = !info->hvm )=0A regs[0] &=3D ~XSAVES;=0A regs[2] &=3D = info->xfeature_mask;=0A- regs[3] =3D 0;=0A+ regs[3] &=3D = info->xfeature_mask >> 32;=0A break;=0A- case 2 ... 63: /* = sub-leaves */=0A+ case 2 ... 62: /* per-component sub-leaves */=0A = if ( !(info->xfeature_mask & (1ULL << input[1])) )=0A {=0A = regs[0] =3D regs[1] =3D regs[2] =3D regs[3] =3D 0;=0A = break;=0A }=0A /* Don't touch EAX, EBX. Also cleanup ECX = and EDX */=0A- regs[2] =3D regs[3] =3D 0;=0A+ regs[2] &=3D = XSTATE_XSS | XSTATE_ALIGN64;=0A+ regs[3] =3D 0;=0A+ = break;=0A+ default:=0A+ regs[0] =3D regs[1] =3D regs[2] =3D = regs[3] =3D 0;=0A break;=0A }=0A }=0A --=__PartAF980523.2__= Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: base64 Content-Disposition: inline X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX18KWGVuLWRldmVs IG1haWxpbmcgbGlzdApYZW4tZGV2ZWxAbGlzdHMueGVuLm9yZwpodHRwOi8vbGlzdHMueGVuLm9y Zy94ZW4tZGV2ZWwK --=__PartAF980523.2__=--