* [PATCH] x86: drop hvm/iommu.h
@ 2016-06-08 13:12 Jan Beulich
2016-06-09 11:35 ` Andrew Cooper
0 siblings, 1 reply; 2+ messages in thread
From: Jan Beulich @ 2016-06-08 13:12 UTC (permalink / raw)
To: xen-devel; +Cc: Andrew Cooper
[-- Attachment #1: Type: text/plain, Size: 3946 bytes --]
As a follow-up to commit af07377007 ("IOMMU/x86: per-domain control
structure is not HVM-specific"), fold hvm/iommu.h into iommu.h.
Signed-off-by: Jan Beulich <jbeulich@suse.com>
--- a/xen/include/asm-x86/hvm/iommu.h
+++ /dev/null
@@ -1,66 +0,0 @@
-#ifndef __ASM_X86_HVM_IOMMU_H__
-#define __ASM_X86_HVM_IOMMU_H__
-
-#include <xen/errno.h>
-
-struct iommu_ops;
-extern const struct iommu_ops intel_iommu_ops;
-extern const struct iommu_ops amd_iommu_ops;
-extern int intel_vtd_setup(void);
-extern int amd_iov_detect(void);
-
-static inline const struct iommu_ops *iommu_get_ops(void)
-{
- switch ( boot_cpu_data.x86_vendor )
- {
- case X86_VENDOR_INTEL:
- return &intel_iommu_ops;
- case X86_VENDOR_AMD:
- return &amd_iommu_ops;
- default:
- BUG();
- }
-
- return NULL;
-}
-
-static inline int iommu_hardware_setup(void)
-{
- switch ( boot_cpu_data.x86_vendor )
- {
- case X86_VENDOR_INTEL:
- return intel_vtd_setup();
- case X86_VENDOR_AMD:
- return amd_iov_detect();
- default:
- return -ENODEV;
- }
-
- return 0;
-}
-
-struct g2m_ioport {
- struct list_head list;
- unsigned int gport;
- unsigned int mport;
- unsigned int np;
-};
-
-#define DEFAULT_DOMAIN_ADDRESS_WIDTH 48
-
-struct arch_iommu
-{
- u64 pgd_maddr; /* io page directory machine address */
- spinlock_t mapping_lock; /* io page table lock */
- int agaw; /* adjusted guest address width, 0 is level 2 30-bit */
- struct list_head g2m_ioport_list; /* guest to machine ioport mapping */
- u64 iommu_bitmap; /* bitmap of iommu(s) that the domain uses */
- struct list_head mapped_rmrrs;
-
- /* amd iommu support */
- int paging_mode;
- struct page_info *root_table;
- struct guest_iommu *g_iommu;
-};
-
-#endif /* __ASM_X86_HVM_IOMMU_H__ */
--- a/xen/include/asm-x86/iommu.h
+++ b/xen/include/asm-x86/iommu.h
@@ -14,10 +14,69 @@
#ifndef __ARCH_X86_IOMMU_H__
#define __ARCH_X86_IOMMU_H__
-#include <asm/hvm/iommu.h> /* For now - should really be merged here. */
+#include <xen/errno.h>
+#include <xen/list.h>
+#include <xen/spinlock.h>
+#include <asm/processor.h>
+#define DEFAULT_DOMAIN_ADDRESS_WIDTH 48
#define MAX_IOMMUS 32
+struct g2m_ioport {
+ struct list_head list;
+ unsigned int gport;
+ unsigned int mport;
+ unsigned int np;
+};
+
+struct arch_iommu
+{
+ u64 pgd_maddr; /* io page directory machine address */
+ spinlock_t mapping_lock; /* io page table lock */
+ int agaw; /* adjusted guest address width, 0 is level 2 30-bit */
+ struct list_head g2m_ioport_list; /* guest to machine ioport mapping */
+ u64 iommu_bitmap; /* bitmap of iommu(s) that the domain uses */
+ struct list_head mapped_rmrrs;
+
+ /* amd iommu support */
+ int paging_mode;
+ struct page_info *root_table;
+ struct guest_iommu *g_iommu;
+};
+
+extern const struct iommu_ops intel_iommu_ops;
+extern const struct iommu_ops amd_iommu_ops;
+int intel_vtd_setup(void);
+int amd_iov_detect(void);
+
+static inline const struct iommu_ops *iommu_get_ops(void)
+{
+ switch ( boot_cpu_data.x86_vendor )
+ {
+ case X86_VENDOR_INTEL:
+ return &intel_iommu_ops;
+ case X86_VENDOR_AMD:
+ return &amd_iommu_ops;
+ }
+
+ BUG();
+
+ return NULL;
+}
+
+static inline int iommu_hardware_setup(void)
+{
+ switch ( boot_cpu_data.x86_vendor )
+ {
+ case X86_VENDOR_INTEL:
+ return intel_vtd_setup();
+ case X86_VENDOR_AMD:
+ return amd_iov_detect();
+ }
+
+ return -ENODEV;
+}
+
/* Does this domain have a P2M table we can use as its IOMMU pagetable? */
#define iommu_use_hap_pt(d) (hap_enabled(d) && iommu_hap_pt_share)
[-- Attachment #2: x86-fold-hvm-iommu-h.patch --]
[-- Type: text/plain, Size: 3965 bytes --]
x86: drop hvm/iommu.h
As a follow-up to commit af07377007 ("IOMMU/x86: per-domain control
structure is not HVM-specific"), fold hvm/iommu.h into iommu.h.
Signed-off-by: Jan Beulich <jbeulich@suse.com>
--- a/xen/include/asm-x86/hvm/iommu.h
+++ /dev/null
@@ -1,66 +0,0 @@
-#ifndef __ASM_X86_HVM_IOMMU_H__
-#define __ASM_X86_HVM_IOMMU_H__
-
-#include <xen/errno.h>
-
-struct iommu_ops;
-extern const struct iommu_ops intel_iommu_ops;
-extern const struct iommu_ops amd_iommu_ops;
-extern int intel_vtd_setup(void);
-extern int amd_iov_detect(void);
-
-static inline const struct iommu_ops *iommu_get_ops(void)
-{
- switch ( boot_cpu_data.x86_vendor )
- {
- case X86_VENDOR_INTEL:
- return &intel_iommu_ops;
- case X86_VENDOR_AMD:
- return &amd_iommu_ops;
- default:
- BUG();
- }
-
- return NULL;
-}
-
-static inline int iommu_hardware_setup(void)
-{
- switch ( boot_cpu_data.x86_vendor )
- {
- case X86_VENDOR_INTEL:
- return intel_vtd_setup();
- case X86_VENDOR_AMD:
- return amd_iov_detect();
- default:
- return -ENODEV;
- }
-
- return 0;
-}
-
-struct g2m_ioport {
- struct list_head list;
- unsigned int gport;
- unsigned int mport;
- unsigned int np;
-};
-
-#define DEFAULT_DOMAIN_ADDRESS_WIDTH 48
-
-struct arch_iommu
-{
- u64 pgd_maddr; /* io page directory machine address */
- spinlock_t mapping_lock; /* io page table lock */
- int agaw; /* adjusted guest address width, 0 is level 2 30-bit */
- struct list_head g2m_ioport_list; /* guest to machine ioport mapping */
- u64 iommu_bitmap; /* bitmap of iommu(s) that the domain uses */
- struct list_head mapped_rmrrs;
-
- /* amd iommu support */
- int paging_mode;
- struct page_info *root_table;
- struct guest_iommu *g_iommu;
-};
-
-#endif /* __ASM_X86_HVM_IOMMU_H__ */
--- a/xen/include/asm-x86/iommu.h
+++ b/xen/include/asm-x86/iommu.h
@@ -14,10 +14,69 @@
#ifndef __ARCH_X86_IOMMU_H__
#define __ARCH_X86_IOMMU_H__
-#include <asm/hvm/iommu.h> /* For now - should really be merged here. */
+#include <xen/errno.h>
+#include <xen/list.h>
+#include <xen/spinlock.h>
+#include <asm/processor.h>
+#define DEFAULT_DOMAIN_ADDRESS_WIDTH 48
#define MAX_IOMMUS 32
+struct g2m_ioport {
+ struct list_head list;
+ unsigned int gport;
+ unsigned int mport;
+ unsigned int np;
+};
+
+struct arch_iommu
+{
+ u64 pgd_maddr; /* io page directory machine address */
+ spinlock_t mapping_lock; /* io page table lock */
+ int agaw; /* adjusted guest address width, 0 is level 2 30-bit */
+ struct list_head g2m_ioport_list; /* guest to machine ioport mapping */
+ u64 iommu_bitmap; /* bitmap of iommu(s) that the domain uses */
+ struct list_head mapped_rmrrs;
+
+ /* amd iommu support */
+ int paging_mode;
+ struct page_info *root_table;
+ struct guest_iommu *g_iommu;
+};
+
+extern const struct iommu_ops intel_iommu_ops;
+extern const struct iommu_ops amd_iommu_ops;
+int intel_vtd_setup(void);
+int amd_iov_detect(void);
+
+static inline const struct iommu_ops *iommu_get_ops(void)
+{
+ switch ( boot_cpu_data.x86_vendor )
+ {
+ case X86_VENDOR_INTEL:
+ return &intel_iommu_ops;
+ case X86_VENDOR_AMD:
+ return &amd_iommu_ops;
+ }
+
+ BUG();
+
+ return NULL;
+}
+
+static inline int iommu_hardware_setup(void)
+{
+ switch ( boot_cpu_data.x86_vendor )
+ {
+ case X86_VENDOR_INTEL:
+ return intel_vtd_setup();
+ case X86_VENDOR_AMD:
+ return amd_iov_detect();
+ }
+
+ return -ENODEV;
+}
+
/* Does this domain have a P2M table we can use as its IOMMU pagetable? */
#define iommu_use_hap_pt(d) (hap_enabled(d) && iommu_hap_pt_share)
[-- Attachment #3: Type: text/plain, Size: 126 bytes --]
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