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From: Julien Grall <julien.grall@arm.com>
To: shankerd@codeaurora.org, Stefano Stabellini <sstabellini@kernel.org>
Cc: Andre Przywara <andre.przywara@arm.com>,
	Philip Elcan <pelcan@codeaurora.org>,
	xen-devel <xen-devel@lists.xensource.com>,
	Vikram Sethi <vikrams@codeaurora.org>,
	Wei Chen <wei.chen@linaro.org>
Subject: Re: [PATCH V9 2/3] drivers/pl011: Use combination of UARTRIS and UARTMSC instead of UARTMIS
Date: Tue, 14 Jun 2016 15:53:01 +0100	[thread overview]
Message-ID: <57601A4D.3070700@arm.com> (raw)
In-Reply-To: <575EF0B5.7050003@codeaurora.org>

Hello Shanker,

On 13/06/16 18:43, Shanker Donthineni wrote:
>
>
> On 06/13/2016 05:30 AM, Stefano Stabellini wrote:
>> On Thu, 9 Jun 2016, Shanker Donthineni wrote:
>>> The Masked interrupt status register (UARTMIS) is not described in ARM
>>> SBSA 2.x document. Anding of two registers UARTMSC and UARTRIS values
>>> gives the same information as register UARTMIS.
>>>
>>> UARTRIS, UARTMSC and UARTMIS definitions are found in PrimeCell UART
>>> PL011 (Revision: r1p4).
>>>   - 3.3.10 Interrupt mask set/clear register, UARTIMSC
>>>   - 3.3.11 Raw interrupt status register, UARTRIS
>>>   - 3.3.12 Masked interrupt status register, UARTMIS
>>>
>>> This change is necessary for driver to be SBSA compliant v2.x without
>>> affecting the current driver functionality.
>>>
>>> Signed-off-by: Shanker Donthineni <shankerd@codeaurora.org>
>>> Reviewed-by: Julien Grall <julien.grall@arm.com>
>>>
>>> Changes since v8:
>>>   Fixed white spaces.
>>>
>>> Changes since v7:
>>>   Moved comment 'To compatible with SBSA v2.x document, all accesses
>> should be 32-bit' to #3
>>> Changes since v1:
>>>   Added a new function to return an interrupt status.
>>>
>>>   xen/drivers/char/pl011.c | 10 ++++++++--
>>>   1 file changed, 8 insertions(+), 2 deletions(-)
>>>
>>> diff --git a/xen/drivers/char/pl011.c b/xen/drivers/char/pl011.c
>>> index 6a3c21b..7e19c4a 100644
>>> --- a/xen/drivers/char/pl011.c
>>> +++ b/xen/drivers/char/pl011.c
>>> @@ -53,11 +53,17 @@ static struct pl011 {
>>>   #define pl011_read(uart, off)           readl((uart)->regs + (off))
>>>   #define pl011_write(uart, off,val)      writel((val), (uart)->regs +
>> (off))
>>> +static unsigned int pl011_intr_status(struct pl011 *uart)
>> Maybe this should be static inline?
>>
>> In any case the series is good, I am happy to queue it up for 4.8.
> Nice discussion on usage of keyword 'inline',
> https://www.kernel.org/doc/local/inline.html.

Well, this page has been created in 2007. GCC may have been fixed since 
then.

Looking at the GCC manual [1]: "GCC does not inline any functions when 
not optimizing unless you specify the ‘always_inline’ attribute for the 
function". Although, non-debug build will always have use optimization 
flags. For debug build, we don't really care about performance so this 
is fine.

Note that without the keyword "inline" GCC may or not may inline the 
function. In the case of this patch, this would result to 2 function 
calls in the interrupt handler. Also, Xen may be built by other 
compilers than GCC (such as Clang) which may require the keyword 
"inline" to effectively inline the function.

Anyway, as mentioned by Stefano this is not that important.

Regards,

[1] https://gcc.gnu.org/onlinedocs/gcc/Inline.html#Inline

-- 
Julien Grall

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  reply	other threads:[~2016-06-14 14:53 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-06-09 17:33 [PATCH V9 1/3] drivers/pl011: Don't configure baudrate Shanker Donthineni
2016-06-09 17:33 ` [PATCH V9 2/3] drivers/pl011: Use combination of UARTRIS and UARTMSC instead of UARTMIS Shanker Donthineni
2016-06-13 10:30   ` Stefano Stabellini
2016-06-13 17:43     ` Shanker Donthineni
2016-06-14 14:53       ` Julien Grall [this message]
2016-06-09 17:33 ` [PATCH V9 3/3] arm/acpi: Add Server Base System Architecture UART support Shanker Donthineni

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