From mboxrd@z Thu Jan 1 00:00:00 1970 From: "Jan Beulich" Subject: [PATCH 5/8] x86/time: correctly honor late clearing of TSC related feature flags Date: Wed, 15 Jun 2016 04:28:52 -0600 Message-ID: <57614A0402000078000F53A5@prv-mh.provo.novell.com> References: <576140F302000078000F52FE@prv-mh.provo.novell.com> Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="=__Part87B1BCF4.1__=" Return-path: Received: from mail6.bemta3.messagelabs.com ([195.245.230.39]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1bD849-0007hZ-3m for xen-devel@lists.xenproject.org; Wed, 15 Jun 2016 10:28:57 +0000 In-Reply-To: <576140F302000078000F52FE@prv-mh.provo.novell.com> List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" To: xen-devel Cc: Andrew Cooper , Dario Faggioli , Joao Martins List-Id: xen-devel@lists.xenproject.org This is a MIME message. If you are reading this text, you may want to consider changing to a mail reader or gateway that understands how to properly handle MIME multipart messages. --=__Part87B1BCF4.1__= Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: quoted-printable Content-Disposition: inline As such clearing of flags may have an impact on the selected rendezvous function, handle such in a central place. But don't allow such feature flags to be cleared during CPU hotplug: Platform and local system times may have diverged significantly by then, potentially causing noticably (even if only temporary) strange behavior. As we're anyway expecting only sufficiently similar CPUs to appear during hotplug, this shouldn't be introducing new limitations. Reported-by: Joao Martins Signed-off-by: Jan Beulich --- a/xen/arch/x86/cpu/mwait-idle.c +++ b/xen/arch/x86/cpu/mwait-idle.c @@ -1135,8 +1135,8 @@ static int mwait_idle_cpu_init(struct no } =20 if (state > 2 && !boot_cpu_has(X86_FEATURE_NONSTOP_TSC) && - !pm_idle_save) - setup_clear_cpu_cap(X86_FEATURE_TSC_RELIABLE); + !pm_idle_save && system_state < SYS_STATE_active) + clear_tsc_cap(X86_FEATURE_TSC_RELIABLE); =20 cx =3D dev->states + dev->count; cx->type =3D state; --- a/xen/arch/x86/time.c +++ b/xen/arch/x86/time.c @@ -1358,6 +1358,24 @@ static void time_calibration(void *unuse &r, 1); } =20 +void __init clear_tsc_cap(unsigned int feature) +{ + void (*rendezvous_fn)(void *) =3D time_calibration_std_rendezvous; + + if ( feature ) + setup_clear_cpu_cap(feature); + + /* If we have constant-rate TSCs then scale factor can be shared. */ + if ( boot_cpu_has(X86_FEATURE_CONSTANT_TSC) ) + { + /* If TSCs are not marked as 'reliable', re-sync during rendezvous= . */ + if ( !boot_cpu_has(X86_FEATURE_TSC_RELIABLE) ) + rendezvous_fn =3D time_calibration_tsc_rendezvous; + } + + time_calibration_rendezvous_fn =3D rendezvous_fn; +} + static struct { s_time_t local_stime, master_stime; } ap_bringup_ref; @@ -1482,7 +1500,7 @@ static int __init verify_tsc_reliability { printk("%s: TSC warp detected, disabling TSC_RELIABLE\n", __func__); - setup_clear_cpu_cap(X86_FEATURE_TSC_RELIABLE); + clear_tsc_cap(X86_FEATURE_TSC_RELIABLE); } } =20 @@ -1495,13 +1513,7 @@ int __init init_xen_time(void) { tsc_check_writability(); =20 - /* If we have constant-rate TSCs then scale factor can be shared. */ - if ( boot_cpu_has(X86_FEATURE_CONSTANT_TSC) ) - { - /* If TSCs are not marked as 'reliable', re-sync during rendezvous= . */ - if ( !boot_cpu_has(X86_FEATURE_TSC_RELIABLE) ) - time_calibration_rendezvous_fn =3D time_calibration_tsc_rendez= vous; - } + clear_tsc_cap(0); =20 open_softirq(TIME_CALIBRATE_SOFTIRQ, local_time_calibration); =20 --- a/xen/include/asm-x86/time.h +++ b/xen/include/asm-x86/time.h @@ -71,6 +71,7 @@ void tsc_get_info(struct domain *d, uint void force_update_vcpu_system_time(struct vcpu *v); =20 int host_tsc_is_safe(void); +void clear_tsc_cap(unsigned int feature); void cpuid_time_leaf(uint32_t sub_idx, uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx); =20 --=__Part87B1BCF4.1__= Content-Type: text/plain; name="x86-time-late-feature-disable.patch" Content-Transfer-Encoding: quoted-printable Content-Disposition: attachment; filename="x86-time-late-feature-disable.patch" x86/time: correctly honor late clearing of TSC related feature flags=0A=0AA= s such clearing of flags may have an impact on the selected rendezvous=0Afu= nction, handle such in a central place.=0A=0ABut don't allow such feature = flags to be cleared during CPU hotplug:=0APlatform and local system times = may have diverged significantly by=0Athen, potentially causing noticably = (even if only temporary) strange=0Abehavior. As we're anyway expecting = only sufficiently similar CPUs to=0Aappear during hotplug, this shouldn't = be introducing new limitations.=0A=0AReported-by: Joao Martins =0ASigned-off-by: Jan Beulich =0A=0A--- = a/xen/arch/x86/cpu/mwait-idle.c=0A+++ b/xen/arch/x86/cpu/mwait-idle.c=0A@@ = -1135,8 +1135,8 @@ static int mwait_idle_cpu_init(struct no=0A = }=0A =0A if (state > 2 && !boot_cpu_has(X86_FEATURE_NONSTOP_= TSC) &&=0A- !pm_idle_save)=0A- setup_clear= _cpu_cap(X86_FEATURE_TSC_RELIABLE);=0A+ !pm_idle_save && = system_state < SYS_STATE_active)=0A+ clear_tsc_cap(X86_F= EATURE_TSC_RELIABLE);=0A =0A cx =3D dev->states + dev->count;=0A= cx->type =3D state;=0A--- a/xen/arch/x86/time.c=0A+++ = b/xen/arch/x86/time.c=0A@@ -1358,6 +1358,24 @@ static void time_calibration= (void *unuse=0A &r, 1);=0A }=0A =0A+void __init = clear_tsc_cap(unsigned int feature)=0A+{=0A+ void (*rendezvous_fn)(void = *) =3D time_calibration_std_rendezvous;=0A+=0A+ if ( feature )=0A+ = setup_clear_cpu_cap(feature);=0A+=0A+ /* If we have constant-rate = TSCs then scale factor can be shared. */=0A+ if ( boot_cpu_has(X86_FEATU= RE_CONSTANT_TSC) )=0A+ {=0A+ /* If TSCs are not marked as = 'reliable', re-sync during rendezvous. */=0A+ if ( !boot_cpu_has(X86= _FEATURE_TSC_RELIABLE) )=0A+ rendezvous_fn =3D time_calibration_= tsc_rendezvous;=0A+ }=0A+=0A+ time_calibration_rendezvous_fn =3D = rendezvous_fn;=0A+}=0A+=0A static struct {=0A s_time_t local_stime, = master_stime;=0A } ap_bringup_ref;=0A@@ -1482,7 +1500,7 @@ static int = __init verify_tsc_reliability=0A {=0A printk("%s: TSC = warp detected, disabling TSC_RELIABLE\n",=0A __func__);= =0A- setup_clear_cpu_cap(X86_FEATURE_TSC_RELIABLE);=0A+ = clear_tsc_cap(X86_FEATURE_TSC_RELIABLE);=0A }=0A }=0A =0A@@ = -1495,13 +1513,7 @@ int __init init_xen_time(void)=0A {=0A tsc_check_wr= itability();=0A =0A- /* If we have constant-rate TSCs then scale factor = can be shared. */=0A- if ( boot_cpu_has(X86_FEATURE_CONSTANT_TSC) )=0A- = {=0A- /* If TSCs are not marked as 'reliable', re-sync during = rendezvous. */=0A- if ( !boot_cpu_has(X86_FEATURE_TSC_RELIABLE) = )=0A- time_calibration_rendezvous_fn =3D time_calibration_tsc_re= ndezvous;=0A- }=0A+ clear_tsc_cap(0);=0A =0A open_softirq(TIME_CA= LIBRATE_SOFTIRQ, local_time_calibration);=0A =0A--- a/xen/include/asm-x86/t= ime.h=0A+++ b/xen/include/asm-x86/time.h=0A@@ -71,6 +71,7 @@ void = tsc_get_info(struct domain *d, uint=0A void force_update_vcpu_system_time(s= truct vcpu *v);=0A =0A int host_tsc_is_safe(void);=0A+void clear_tsc_cap(un= signed int feature);=0A void cpuid_time_leaf(uint32_t sub_idx, uint32_t = *eax, uint32_t *ebx,=0A uint32_t *ecx, uint32_t = *edx);=0A =0A --=__Part87B1BCF4.1__= Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: base64 Content-Disposition: inline X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX18KWGVuLWRldmVs IG1haWxpbmcgbGlzdApYZW4tZGV2ZWxAbGlzdHMueGVuLm9yZwpodHRwOi8vbGlzdHMueGVuLm9y Zy94ZW4tZGV2ZWwK --=__Part87B1BCF4.1__=--