From mboxrd@z Thu Jan 1 00:00:00 1970 From: "Jan Beulich" Subject: [PATCH 2/2] hvmloader: don't hard-code IO-APIC parameters Date: Thu, 16 Jun 2016 03:40:43 -0600 Message-ID: <5762903B02000078000F597E@prv-mh.provo.novell.com> References: <57628EA302000078000F596B@prv-mh.provo.novell.com> Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="=__Part22141A0B.1__=" Return-path: Received: from mail6.bemta5.messagelabs.com ([195.245.231.135]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1bDTn6-0006qw-O1 for xen-devel@lists.xenproject.org; Thu, 16 Jun 2016 09:40:48 +0000 In-Reply-To: <57628EA302000078000F596B@prv-mh.provo.novell.com> List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" To: xen-devel Cc: Andrew Cooper List-Id: xen-devel@lists.xenproject.org This is a MIME message. If you are reading this text, you may want to consider changing to a mail reader or gateway that understands how to properly handle MIME multipart messages. --=__Part22141A0B.1__= Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: quoted-printable Content-Disposition: inline The IO-APIC address has variable bits determined by the PCI-to-ISA bridge, and the IO-APIC version should be read from the IO-APIC. (Note that there's still implicit rather than explicit agreement on the IO-APIC base address between qemu and the hypervisor.) Signed-off-by: Jan Beulich --- a/tools/firmware/hvmloader/acpi/build.c +++ b/tools/firmware/hvmloader/acpi/build.c @@ -138,7 +138,7 @@ static struct acpi_20_madt *construct_ma io_apic->type =3D ACPI_IO_APIC; io_apic->length =3D sizeof(*io_apic); io_apic->ioapic_id =3D IOAPIC_ID; - io_apic->ioapic_addr =3D IOAPIC_BASE_ADDRESS; + io_apic->ioapic_addr =3D ioapic_base_address; =20 lapic =3D (struct acpi_20_madt_lapic *)(io_apic + 1); info->nr_cpus =3D hvm_info->nr_vcpus; --- a/tools/firmware/hvmloader/config.h +++ b/tools/firmware/hvmloader/config.h @@ -42,9 +42,10 @@ extern struct bios_config ovmf_config; #define PAGE_SHIFT 12 #define PAGE_SIZE (1ul << PAGE_SHIFT) =20 -#define IOAPIC_BASE_ADDRESS 0xfec00000 +extern uint32_t ioapic_base_address; +extern uint8_t ioapic_version; + #define IOAPIC_ID 0x01 -#define IOAPIC_VERSION 0x11 =20 #define LAPIC_BASE_ADDRESS 0xfee00000 #define LAPIC_ID(vcpu_id) ((vcpu_id) * 2) --- a/tools/firmware/hvmloader/hvmloader.c +++ b/tools/firmware/hvmloader/hvmloader.c @@ -108,6 +108,9 @@ asm ( =20 unsigned long scratch_start =3D SCRATCH_PHYSICAL_ADDRESS; =20 +uint32_t ioapic_base_address =3D 0xfec00000; +uint8_t ioapic_version; + static void init_hypercalls(void) { uint32_t eax, ebx, ecx, edx; @@ -185,6 +188,9 @@ static void init_vm86_tss(void) =20 static void apic_setup(void) { + ioapic_base_address |=3D (pci_readb(PCI_ISA_DEVFN, 0x80) & 0x3f) << = 10; + ioapic_version =3D ioapic_read(0x01) & 0xff; + /* Set the IOAPIC ID to the static value used in the MP/ACPI tables. = */ ioapic_write(0x00, IOAPIC_ID); =20 --- a/tools/firmware/hvmloader/mp_tables.c +++ b/tools/firmware/hvmloader/mp_tables.c @@ -227,9 +227,9 @@ static void fill_mp_ioapic_entry(struct { mpie->type =3D ENTRY_TYPE_IOAPIC; mpie->ioapic_id =3D IOAPIC_ID; - mpie->ioapic_version =3D IOAPIC_VERSION; + mpie->ioapic_version =3D ioapic_version; mpie->ioapic_flags =3D 1; /* enabled */ - mpie->ioapic_addr =3D IOAPIC_BASE_ADDRESS; + mpie->ioapic_addr =3D ioapic_base_address; } =20 =20 --- a/tools/firmware/hvmloader/util.c +++ b/tools/firmware/hvmloader/util.c @@ -490,14 +490,14 @@ void *scratch_alloc(uint32_t size, uint3 =20 uint32_t ioapic_read(uint32_t reg) { - *(volatile uint32_t *)(IOAPIC_BASE_ADDRESS + 0x00) =3D reg; - return *(volatile uint32_t *)(IOAPIC_BASE_ADDRESS + 0x10); + *(volatile uint32_t *)(ioapic_base_address + 0x00) =3D reg; + return *(volatile uint32_t *)(ioapic_base_address + 0x10); } =20 void ioapic_write(uint32_t reg, uint32_t val) { - *(volatile uint32_t *)(IOAPIC_BASE_ADDRESS + 0x00) =3D reg; - *(volatile uint32_t *)(IOAPIC_BASE_ADDRESS + 0x10) =3D val; + *(volatile uint32_t *)(ioapic_base_address + 0x00) =3D reg; + *(volatile uint32_t *)(ioapic_base_address + 0x10) =3D val; } =20 uint32_t lapic_read(uint32_t reg) --=__Part22141A0B.1__= Content-Type: text/plain; name="hvmloader-IOAPIC-settings.patch" Content-Transfer-Encoding: quoted-printable Content-Disposition: attachment; filename="hvmloader-IOAPIC-settings.patch" hvmloader: don't hard-code IO-APIC parameters=0A=0AThe IO-APIC address has = variable bits determined by the PCI-to-ISA=0Abridge, and the IO-APIC = version should be read from the IO-APIC. (Note=0Athat there's still = implicit rather than explicit agreement on the=0AIO-APIC base address = between qemu and the hypervisor.)=0A=0ASigned-off-by: Jan Beulich = =0A=0A--- a/tools/firmware/hvmloader/acpi/build.c=0A+++ = b/tools/firmware/hvmloader/acpi/build.c=0A@@ -138,7 +138,7 @@ static = struct acpi_20_madt *construct_ma=0A io_apic->type =3D = ACPI_IO_APIC;=0A io_apic->length =3D sizeof(*io_apic);=0A = io_apic->ioapic_id =3D IOAPIC_ID;=0A- io_apic->ioapic_addr =3D = IOAPIC_BASE_ADDRESS;=0A+ io_apic->ioapic_addr =3D ioapic_base_address;= =0A =0A lapic =3D (struct acpi_20_madt_lapic *)(io_apic + 1);=0A = info->nr_cpus =3D hvm_info->nr_vcpus;=0A--- a/tools/firmware/hvmloader/conf= ig.h=0A+++ b/tools/firmware/hvmloader/config.h=0A@@ -42,9 +42,10 @@ extern = struct bios_config ovmf_config;=0A #define PAGE_SHIFT 12=0A #define = PAGE_SIZE (1ul << PAGE_SHIFT)=0A =0A-#define IOAPIC_BASE_ADDRESS = 0xfec00000=0A+extern uint32_t ioapic_base_address;=0A+extern uint8_t = ioapic_version;=0A+=0A #define IOAPIC_ID 0x01=0A-#define = IOAPIC_VERSION 0x11=0A =0A #define LAPIC_BASE_ADDRESS 0xfee00000=0A = #define LAPIC_ID(vcpu_id) ((vcpu_id) * 2)=0A--- a/tools/firmware/hvmloade= r/hvmloader.c=0A+++ b/tools/firmware/hvmloader/hvmloader.c=0A@@ -108,6 = +108,9 @@ asm (=0A =0A unsigned long scratch_start =3D SCRATCH_PHYSICAL_ADD= RESS;=0A =0A+uint32_t ioapic_base_address =3D 0xfec00000;=0A+uint8_t = ioapic_version;=0A+=0A static void init_hypercalls(void)=0A {=0A = uint32_t eax, ebx, ecx, edx;=0A@@ -185,6 +188,9 @@ static void init_vm86_ts= s(void)=0A =0A static void apic_setup(void)=0A {=0A+ ioapic_base_address= |=3D (pci_readb(PCI_ISA_DEVFN, 0x80) & 0x3f) << 10;=0A+ ioapic_version = =3D ioapic_read(0x01) & 0xff;=0A+=0A /* Set the IOAPIC ID to the = static value used in the MP/ACPI tables. */=0A ioapic_write(0x00, = IOAPIC_ID);=0A =0A--- a/tools/firmware/hvmloader/mp_tables.c=0A+++ = b/tools/firmware/hvmloader/mp_tables.c=0A@@ -227,9 +227,9 @@ static void = fill_mp_ioapic_entry(struct=0A {=0A mpie->type =3D ENTRY_TYPE_IOAPIC;= =0A mpie->ioapic_id =3D IOAPIC_ID;=0A- mpie->ioapic_version =3D = IOAPIC_VERSION;=0A+ mpie->ioapic_version =3D ioapic_version;=0A = mpie->ioapic_flags =3D 1; /* enabled */=0A- mpie->ioapic_addr =3D = IOAPIC_BASE_ADDRESS;=0A+ mpie->ioapic_addr =3D ioapic_base_address;=0A = }=0A =0A =0A--- a/tools/firmware/hvmloader/util.c=0A+++ b/tools/firmware/hv= mloader/util.c=0A@@ -490,14 +490,14 @@ void *scratch_alloc(uint32_t size, = uint3=0A =0A uint32_t ioapic_read(uint32_t reg)=0A {=0A- *(volatile = uint32_t *)(IOAPIC_BASE_ADDRESS + 0x00) =3D reg;=0A- return *(volatile = uint32_t *)(IOAPIC_BASE_ADDRESS + 0x10);=0A+ *(volatile uint32_t = *)(ioapic_base_address + 0x00) =3D reg;=0A+ return *(volatile uint32_t = *)(ioapic_base_address + 0x10);=0A }=0A =0A void ioapic_write(uint32_t = reg, uint32_t val)=0A {=0A- *(volatile uint32_t *)(IOAPIC_BASE_ADDRESS = + 0x00) =3D reg;=0A- *(volatile uint32_t *)(IOAPIC_BASE_ADDRESS + 0x10) = =3D val;=0A+ *(volatile uint32_t *)(ioapic_base_address + 0x00) =3D = reg;=0A+ *(volatile uint32_t *)(ioapic_base_address + 0x10) =3D val;=0A = }=0A =0A uint32_t lapic_read(uint32_t reg)=0A --=__Part22141A0B.1__= Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: base64 Content-Disposition: inline X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX18KWGVuLWRldmVs IG1haWxpbmcgbGlzdApYZW4tZGV2ZWxAbGlzdHMueGVuLm9yZwpodHRwOi8vbGlzdHMueGVuLm9y Zy94ZW4tZGV2ZWwK --=__Part22141A0B.1__=--