From: "Jan Beulich" <JBeulich@suse.com>
To: Andrew Cooper <andrew.cooper3@citrix.com>
Cc: Lan Tianyu <tianyu.lan@intel.com>,
Sergey Dyasli <sergey.dyasli@citrix.com>,
Kevin Tian <kevin.tian@intel.com>,
StefanoStabellini <sstabellini@kernel.org>,
Wei Liu <wei.liu2@citrix.com>, Juergen Gross <jgross@suse.com>,
George Dunlap <George.Dunlap@eu.citrix.com>,
TimDeegan <tim@xen.org>, Anshul Makkar <anshul.makkar@citrix.com>,
IanJackson <ian.jackson@eu.citrix.com>,
Xen-devel <xen-devel@lists.xen.org>,
Euan Harris <euan.harris@citrix.com>,
JoaoMartins <joao.m.martins@oracle.com>,
Boris Ostrovsky <boris.ostrovsky@oracle.com>,
PaulC Lai <paul.c.lai@intel.com>
Subject: Re: DESIGN: CPUID part 3
Date: Mon, 12 Jun 2017 08:18:22 -0600 [thread overview]
Message-ID: <593EBECE0200007800162072@prv-mh.provo.novell.com> (raw)
In-Reply-To: <607f9093-05ca-c321-8702-cc3bd1795425@citrix.com>
>>> On 12.06.17 at 16:02, <andrew.cooper3@citrix.com> wrote:
> My original statement was "if the guest uses LBR/LER, then migration
> needs to be restricted to hardware with an identical LBR format".
>
> You countered that, saying we could emulate LBR/LER as an alternative.
> The implication here is that we could alter the LBR format via
> emulation, by cooking the value observed when the guest reads the LBR MSRs.
>
> For the record, the formats are:
>
> Software should query an architectural MSR IA32_PERF_CAPABILITIES[5:0]
> about the format of the address that is stored in the LBR stack. Four
> formats are defined by the following encoding:
> * 000000B (32-bit record format) — Stores 32-bit offset in current CS of
> respective source/destination,
> * 000001B (64-bit LIP record format) — Stores 64-bit linear address of
> respective source/destination,
> * 000010B (64-bit EIP record format) — Stores 64-bit offset (effective
> address) of respective source/destination.
> * 000011B (64-bit EIP record format) and Flags — Stores 64-bit offset
> (effective address) of respective source/destination. Misprediction info
> is reported in the upper bit of 'FROM' registers in the LBR stack. See
> LBR stack details below for flag support and definition.
> * 000100B (64-bit EIP record format), Flags and TSX — Stores 64-bit
> offset (effective address) of respective source/destination.
> Misprediction and TSX info are reported in the upper bits of ‘FROM’
> registers in the LBR stack.
> * 000101B (64-bit EIP record format), Flags, TSX, LBR_INFO — Stores
> 64-bit offset (effective address) of respective source/destination.
> Misprediction, TSX, and elapsed cycles since the last LBR update are
> reported in the LBR_INFO MSR stack.
> * 000110B (64-bit EIP record format), Flags, Cycles — Stores 64-bit
> linear address (CS.Base + effective address) of respective
> source/destination. Misprediction info is reported in the upper bits of
> 17-16 Vol. 3BDEBUG, BRANCH PROFILE, TSC, AND RESOURCE MONITORING
> FEATURES 'FROM' registers in the LBR stack. Elapsed cycles since the
> last LBR update are reported in the upper 16 bits of the 'TO' registers
> in the LBR stack (see Section 17.6).
>
> In general, I don't see any sensible way of being able to convert
> between these formats at the point of an RDMSR.
Hmm, I don't see a problem converting formats 3..6 to formats 0
or 2. I also don't think any misbehavior can possibly result when
converting 2 to 3 by simply always loading a fixed value into the
mis-prediction bit. Whether 2 can be converted sensibly to 4..6
would need to be determined. Format 1 clearly is the odd one out,
conversion to/from which would only be reasonable if we assumed
flat addressing everywhere (which obviously we can assume as
long as a guest stays in 64-bit mode).
It is also clear that format 6 won't survive the addition of 5-level
page tables, as there aren't enough bits to store a meaningful
cycle count.
Jan
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next prev parent reply other threads:[~2017-06-12 14:18 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-06-08 13:12 DESIGN: CPUID part 3 Andrew Cooper
2017-06-08 13:47 ` Jan Beulich
2017-06-12 13:07 ` Andrew Cooper
2017-06-12 13:29 ` Jan Beulich
2017-06-12 13:36 ` Andrew Cooper
2017-06-12 13:42 ` Jan Beulich
2017-06-12 14:02 ` Andrew Cooper
2017-06-12 14:18 ` Jan Beulich [this message]
2017-06-09 12:24 ` Anshul Makkar
2017-06-12 13:21 ` Andrew Cooper
2017-07-04 14:55 ` DESIGN v2: " Andrew Cooper
2017-07-05 9:46 ` Joao Martins
2017-07-05 10:32 ` Joao Martins
2017-07-05 11:16 ` Andrew Cooper
2017-07-05 13:22 ` Joao Martins
2017-07-31 19:49 ` Konrad Rzeszutek Wilk
2017-08-01 18:34 ` Andrew Cooper
2017-08-02 10:34 ` Joao Martins
2017-08-03 2:55 ` Dario Faggioli
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