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From: "Jan Beulich" <JBeulich@suse.com>
To: xen-devel <xen-devel@lists.xenproject.org>
Cc: George Dunlap <George.Dunlap@eu.citrix.com>,
	Andrew Cooper <andrew.cooper3@citrix.com>,
	Wei Liu <wei.liu2@citrix.com>
Subject: [PATCH v4 05/44] x86emul: support basic AVX512 moves
Date: Tue, 25 Sep 2018 07:28:49 -0600
Message-ID: <5BAA381102000078001EB9EC@prv1-mh.provo.novell.com> (raw)
In-Reply-To: <5BAA34B502000078001EB9B6@prv1-mh.provo.novell.com>

Note: SDM Vol 2 rev 067 is not really consistent about EVEX.L'L for LIG
      insns - the only place where this is made explicit is a table in
      the section titled "Vector Length Orthogonality": While they
      tolerate 0, 1, and 2, a value of 3 uniformly leads to #UD.

Signed-off-by: Jan Beulich <jbeulich@suse.com>
---
v4: Introduce d8s_dq64 to deal with 32-bit mode VMOVD with EVEX.W set.
    Adjust a comment.
v3: Restrict k-reg reading to insns with memory operand. Shrink scope of
    "disp8scale".
v2: Move "full" into more narrow scope.

--- a/tools/tests/x86_emulator/test_x86_emulator.c
+++ b/tools/tests/x86_emulator/test_x86_emulator.c
@@ -1985,6 +1985,53 @@ int main(int argc, char **argv)
     else
         printf("skipped\n");
 
+    printf("%-40s", "Testing {evex} vmovq %xmm1,32(%edx)...");
+    if ( stack_exec && cpu_has_avx512f )
+    {
+        decl_insn(evex_vmovq_to_mem);
+
+        asm volatile ( "pcmpgtb %%xmm1, %%xmm1\n"
+                       put_insn(evex_vmovq_to_mem, "%{evex%} vmovq %%xmm1, 32(%0)")
+                       :: "d" (NULL) );
+
+        memset(res, 0xdb, 64);
+        set_insn(evex_vmovq_to_mem);
+        regs.ecx = 0;
+        regs.edx = (unsigned long)res;
+        rc = x86_emulate(&ctxt, &emulops);
+        if ( rc != X86EMUL_OKAY || !check_eip(evex_vmovq_to_mem) ||
+             *((uint64_t *)res + 4) ||
+             memcmp(res, res + 10, 24) ||
+             memcmp(res, res + 6, 8) )
+            goto fail;
+        printf("okay\n");
+    }
+    else
+        printf("skipped\n");
+
+    printf("%-40s", "Testing {evex} vmovq 32(%edx),%xmm0...");
+    if ( stack_exec && cpu_has_avx512f )
+    {
+        decl_insn(evex_vmovq_from_mem);
+
+        asm volatile ( "pcmpeqb %%xmm0, %%xmm0\n"
+                       put_insn(evex_vmovq_from_mem, "%{evex%} vmovq 32(%0), %%xmm0")
+                       :: "d" (NULL) );
+
+        set_insn(evex_vmovq_from_mem);
+        rc = x86_emulate(&ctxt, &emulops);
+        if ( rc != X86EMUL_OKAY || !check_eip(evex_vmovq_from_mem) )
+            goto fail;
+        asm ( "vmovq %1, %%xmm1\n\t"
+              "vpcmpeqq %%zmm0, %%zmm1, %%k0\n"
+              "kmovw %%k0, %0" : "=r" (rc) : "m" (res[8]) );
+        if ( rc != 0xff )
+            goto fail;
+        printf("okay\n");
+    }
+    else
+        printf("skipped\n");
+
     printf("%-40s", "Testing movdqu %xmm2,(%ecx)...");
     if ( stack_exec && cpu_has_sse2 )
     {
@@ -2085,6 +2132,118 @@ int main(int argc, char **argv)
     else
         printf("skipped\n");
 
+    printf("%-40s", "Testing vmovdqu32 %zmm2,(%ecx){%k1}...");
+    if ( stack_exec && cpu_has_avx512f )
+    {
+        decl_insn(vmovdqu32_to_mem);
+
+        memset(res, 0x55, 128);
+
+        asm volatile ( "vpcmpeqd %%ymm2, %%ymm2, %%ymm2\n\t"
+                       "kmovw %1,%%k1\n"
+                       put_insn(vmovdqu32_to_mem,
+                                "vmovdqu32 %%zmm2, (%0)%{%%k1%}")
+                       :: "c" (NULL), "rm" (res[0]) );
+        set_insn(vmovdqu32_to_mem);
+
+        regs.ecx = (unsigned long)res;
+        rc = x86_emulate(&ctxt, &emulops);
+        if ( (rc != X86EMUL_OKAY) || memcmp(res + 16, res + 24, 32) ||
+             !check_eip(vmovdqu32_to_mem) )
+            goto fail;
+
+        res[16] = ~0; res[18] = ~0; res[20] = ~0; res[22] = ~0;
+        res[24] =  0; res[26] =  0; res[28] =  0; res[30] =  0;
+        if ( memcmp(res, res + 16, 64) )
+            goto fail;
+
+        printf("okay\n");
+    }
+    else
+        printf("skipped\n");
+
+    printf("%-40s", "Testing vmovdqu32 64(%edx),%zmm2{%k2}...");
+    if ( stack_exec && cpu_has_avx512f )
+    {
+        decl_insn(vmovdqu32_from_mem);
+
+        asm volatile ( "knotw %%k1, %%k2\n"
+                       put_insn(vmovdqu32_from_mem,
+                                "vmovdqu32 64(%0), %%zmm2%{%%k2%}")
+                       :: "d" (NULL) );
+
+        set_insn(vmovdqu32_from_mem);
+        regs.ecx = 0;
+        regs.edx = (unsigned long)res;
+        rc = x86_emulate(&ctxt, &emulops);
+        if ( rc != X86EMUL_OKAY || !check_eip(vmovdqu32_from_mem) )
+            goto fail;
+        asm ( "vpcmpeqd %1, %%zmm2, %%k0\n\t"
+              "kmovw %%k0, %0" : "=r" (rc) : "m" (res[0]) );
+        if ( rc != 0xffff )
+            goto fail;
+        printf("okay\n");
+    }
+    else
+        printf("skipped\n");
+
+    printf("%-40s", "Testing vmovdqu16 %zmm3,(%ecx){%k1}...");
+    if ( stack_exec && cpu_has_avx512bw )
+    {
+        decl_insn(vmovdqu16_to_mem);
+
+        memset(res, 0x55, 128);
+
+        asm volatile ( "vpcmpeqw %%ymm3, %%ymm3, %%ymm3\n\t"
+                       "kmovd %1,%%k1\n"
+                       put_insn(vmovdqu16_to_mem,
+                                "vmovdqu16 %%zmm3, (%0)%{%%k1%}")
+                       :: "c" (NULL), "rm" (res[0]) );
+        set_insn(vmovdqu16_to_mem);
+
+        regs.ecx = (unsigned long)res;
+        rc = x86_emulate(&ctxt, &emulops);
+        if ( (rc != X86EMUL_OKAY) || memcmp(res + 16, res + 24, 32) ||
+             !check_eip(vmovdqu16_to_mem) )
+            goto fail;
+
+        for ( i = 16; i < 24; ++i )
+            res[i] |= 0x0000ffff;
+        for ( ; i < 32; ++i )
+            res[i] &= 0xffff0000;
+        if ( memcmp(res, res + 16, 64) )
+            goto fail;
+
+        printf("okay\n");
+    }
+    else
+        printf("skipped\n");
+
+    printf("%-40s", "Testing vmovdqu16 64(%edx),%zmm3{%k2}...");
+    if ( stack_exec && cpu_has_avx512bw )
+    {
+        decl_insn(vmovdqu16_from_mem);
+
+        asm volatile ( "knotd %%k1, %%k2\n"
+                       put_insn(vmovdqu16_from_mem,
+                                "vmovdqu16 64(%0), %%zmm3%{%%k2%}")
+                       :: "d" (NULL) );
+
+        set_insn(vmovdqu16_from_mem);
+        regs.ecx = 0;
+        regs.edx = (unsigned long)res;
+        rc = x86_emulate(&ctxt, &emulops);
+        if ( rc != X86EMUL_OKAY || !check_eip(vmovdqu16_from_mem) )
+            goto fail;
+        asm ( "vpcmpeqw %1, %%zmm3, %%k0\n\t"
+              "kmovd %%k0, %0" : "=r" (rc) : "m" (res[0]) );
+        if ( rc != 0xffffffff )
+            goto fail;
+        printf("okay\n");
+    }
+    else
+        printf("skipped\n");
+
     printf("%-40s", "Testing movsd %xmm5,(%ecx)...");
     memset(res, 0x77, 64);
     memset(res + 10, 0x66, 8);
@@ -2186,6 +2345,71 @@ int main(int argc, char **argv)
     else
         printf("skipped\n");
 
+    printf("%-40s", "Testing vmovsd %xmm5,16(%ecx){%k3}...");
+    memset(res, 0x88, 128);
+    memset(res + 20, 0x77, 8);
+    if ( stack_exec && cpu_has_avx512f )
+    {
+        decl_insn(vmovsd_masked_to_mem);
+
+        asm volatile ( "vbroadcastsd %0, %%ymm5\n\t"
+                       "kxorw %%k3, %%k3, %%k3\n"
+                       put_insn(vmovsd_masked_to_mem,
+                                "vmovsd %%xmm5, 16(%1)%{%%k3%}")
+                       :: "m" (res[20]), "c" (NULL) );
+
+        set_insn(vmovsd_masked_to_mem);
+        regs.ecx = 0;
+        regs.edx = 0;
+        rc = x86_emulate(&ctxt, &emulops);
+        if ( (rc != X86EMUL_OKAY) || !check_eip(vmovsd_masked_to_mem) )
+            goto fail;
+
+        asm volatile ( "kmovw %0, %%k3\n" :: "m" (res[20]) );
+
+        set_insn(vmovsd_masked_to_mem);
+        regs.ecx = (unsigned long)res;
+        rc = x86_emulate(&ctxt, &emulops);
+        if ( (rc != X86EMUL_OKAY) || !check_eip(vmovsd_masked_to_mem) ||
+             memcmp(res, res + 16, 64) )
+            goto fail;
+
+        printf("okay\n");
+    }
+    else
+    {
+        printf("skipped\n");
+        memset(res + 4, 0x77, 8);
+    }
+
+    printf("%-40s", "Testing vmovaps (%edx),%zmm7{%k3}{z}...");
+    if ( stack_exec && cpu_has_avx512f )
+    {
+        decl_insn(vmovaps_masked_from_mem);
+
+        asm volatile ( "vpcmpeqd %%xmm7, %%xmm7, %%xmm7\n\t"
+                       "vbroadcastss %%xmm7, %%zmm7\n"
+                       put_insn(vmovaps_masked_from_mem,
+                                "vmovaps (%0), %%zmm7%{%%k3%}%{z%}")
+                       :: "d" (NULL) );
+
+        set_insn(vmovaps_masked_from_mem);
+        regs.edx = (unsigned long)res;
+        rc = x86_emulate(&ctxt, &emulops);
+        if ( rc != X86EMUL_OKAY || !check_eip(vmovaps_masked_from_mem) )
+            goto fail;
+        asm ( "vcmpeqps %1, %%zmm7, %%k0\n\t"
+              "vxorps %%xmm0, %%xmm0, %%xmm0\n\t"
+              "vcmpeqps %%zmm0, %%zmm7, %%k1\n\t"
+              "kxorw %%k1, %%k0, %%k0\n\t"
+              "kmovw %%k0, %0" : "=r" (rc) : "m" (res[16]) );
+        if ( rc != 0xffff )
+            goto fail;
+        printf("okay\n");
+    }
+    else
+        printf("skipped\n");
+
     printf("%-40s", "Testing movd %mm3,32(%ecx)...");
     if ( stack_exec && cpu_has_mmx )
     {
@@ -2341,6 +2565,55 @@ int main(int argc, char **argv)
     else
         printf("skipped\n");
 
+    printf("%-40s", "Testing {evex} vmovd %xmm3,32(%ecx)...");
+    if ( stack_exec && cpu_has_avx512f )
+    {
+        decl_insn(evex_vmovd_to_mem);
+
+        asm volatile ( "pcmpeqb %%xmm3, %%xmm3\n"
+                       put_insn(evex_vmovd_to_mem,
+                                "%{evex%} vmovd %%xmm3, 32(%0)")
+                       :: "c" (NULL) );
+
+        memset(res, 0xbd, 64);
+        set_insn(evex_vmovd_to_mem);
+        regs.ecx = (unsigned long)res;
+        regs.edx = 0;
+        rc = x86_emulate(&ctxt, &emulops);
+        if ( rc != X86EMUL_OKAY || !check_eip(evex_vmovd_to_mem) ||
+             res[8] + 1 ||
+             memcmp(res, res + 9, 28) ||
+             memcmp(res, res + 6, 8) )
+            goto fail;
+        printf("okay\n");
+    }
+    else
+        printf("skipped\n");
+
+    printf("%-40s", "Testing {evex} vmovd 32(%ecx),%xmm4...");
+    if ( stack_exec && cpu_has_avx512f )
+    {
+        decl_insn(evex_vmovd_from_mem);
+
+        asm volatile ( "pcmpeqb %%xmm4, %%xmm4\n"
+                       put_insn(evex_vmovd_from_mem,
+                                "%{evex%} vmovd 32(%0), %%xmm4")
+                       :: "c" (NULL) );
+
+        set_insn(evex_vmovd_from_mem);
+        rc = x86_emulate(&ctxt, &emulops);
+        if ( rc != X86EMUL_OKAY || !check_eip(evex_vmovd_from_mem) )
+            goto fail;
+        asm ( "vmovd %1, %%xmm0\n\t"
+              "vpcmpeqd %%zmm4, %%zmm0, %%k0\n\t"
+              "kmovw %%k0, %0" : "=r" (rc) : "m" (res[8]) );
+        if ( rc != 0xffff )
+            goto fail;
+        printf("okay\n");
+    }
+    else
+        printf("skipped\n");
+
     printf("%-40s", "Testing movd %mm3,%ebx...");
     if ( stack_exec && cpu_has_mmx )
     {
@@ -2507,6 +2780,57 @@ int main(int argc, char **argv)
     else
         printf("skipped\n");
 
+    printf("%-40s", "Testing {evex} vmovd %xmm2,%ebx...");
+    if ( stack_exec && cpu_has_avx512f )
+    {
+        decl_insn(evex_vmovd_to_reg);
+
+        /* See comment next to movd above. */
+        asm volatile ( "pcmpeqb %%xmm2, %%xmm2\n"
+                       put_insn(evex_vmovd_to_reg,
+                                "%{evex%} vmovd %%xmm2, %%ebx")
+                       :: );
+
+        set_insn(evex_vmovd_to_reg);
+#ifdef __x86_64__
+        regs.rbx = 0xbdbdbdbdbdbdbdbdUL;
+#else
+        regs.ebx = 0xbdbdbdbdUL;
+#endif
+        rc = x86_emulate(&ctxt, &emulops);
+        if ( (rc != X86EMUL_OKAY) || !check_eip(evex_vmovd_to_reg) ||
+             regs.ebx != 0xffffffff )
+            goto fail;
+        printf("okay\n");
+    }
+    else
+        printf("skipped\n");
+
+    printf("%-40s", "Testing {evex} vmovd %ebx,%xmm1...");
+    if ( stack_exec && cpu_has_avx512f )
+    {
+        decl_insn(evex_vmovd_from_reg);
+
+        /* See comment next to movd above. */
+        asm volatile ( "pcmpgtb %%xmm1, %%xmm1\n"
+                       put_insn(evex_vmovd_from_reg,
+                                "%{evex%} vmovd %%ebx, %%xmm1")
+                       :: );
+
+        set_insn(evex_vmovd_from_reg);
+        rc = x86_emulate(&ctxt, &emulops);
+        if ( (rc != X86EMUL_OKAY) || !check_eip(evex_vmovd_from_reg) )
+            goto fail;
+        asm ( "vmovd %1, %%xmm0\n\t"
+              "vpcmpeqd %%zmm1, %%zmm0, %%k0\n\t"
+              "kmovw %%k0, %0" : "=r" (rc) : "m" (res[8]) );
+        if ( rc != 0xffff )
+            goto fail;
+        printf("okay\n");
+    }
+    else
+        printf("skipped\n");
+
 #ifdef __x86_64__
     printf("%-40s", "Testing movq %mm3,32(%ecx)...");
     if ( stack_exec && cpu_has_mmx )
@@ -2584,6 +2908,36 @@ int main(int argc, char **argv)
     else
         printf("skipped\n");
 
+    printf("%-40s", "Testing {evex} vmovq %xmm11,32(%ecx)...");
+    if ( stack_exec && cpu_has_avx512f )
+    {
+        decl_insn(evex_vmovq_to_mem2);
+
+        asm volatile ( "pcmpeqb %%xmm11, %%xmm11\n"
+#if 0 /* This may not work, as the assembler might pick opcode D6. */
+                       put_insn(evex_vmovq_to_mem2,
+                                "{evex} vmovq %%xmm11, 32(%0)")
+#else
+                       put_insn(evex_vmovq_to_mem2,
+                                ".byte 0x62, 0xf1, 0xfd, 0x08, 0x7e, 0x49, 0x04")
+#endif
+                       :: "c" (NULL) );
+
+        memset(res, 0xbd, 64);
+        set_insn(evex_vmovq_to_mem2);
+        regs.ecx = (unsigned long)res;
+        regs.edx = 0;
+        rc = x86_emulate(&ctxt, &emulops);
+        if ( rc != X86EMUL_OKAY || !check_eip(evex_vmovq_to_mem2) ||
+             *((long *)res + 4) + 1 ||
+             memcmp(res, res + 10, 24) ||
+             memcmp(res, res + 6, 8) )
+            goto fail;
+        printf("okay\n");
+    }
+    else
+        printf("skipped\n");
+
     printf("%-40s", "Testing movq %mm3,%rbx...");
     if ( stack_exec && cpu_has_mmx )
     {
@@ -2643,6 +2997,28 @@ int main(int argc, char **argv)
     }
     else
         printf("skipped\n");
+
+    printf("%-40s", "Testing vmovq %xmm22,%rbx...");
+    if ( stack_exec && cpu_has_avx512f )
+    {
+        decl_insn(evex_vmovq_to_reg);
+
+        /* See comment next to movd above. */
+        asm volatile ( "pcmpeqq %%xmm2, %%xmm2\n\t"
+                       "vmovq %%xmm2, %%xmm22\n"
+                       put_insn(evex_vmovq_to_reg, "vmovq %%xmm22, %%rbx")
+                       :: );
+
+        set_insn(evex_vmovq_to_reg);
+        regs.rbx = 0xbdbdbdbdbdbdbdbdUL;
+        rc = x86_emulate(&ctxt, &emulops);
+        if ( rc != X86EMUL_OKAY || !check_eip(evex_vmovq_to_reg) ||
+             regs.rbx + 1 )
+            goto fail;
+        printf("okay\n");
+    }
+    else
+        printf("skipped\n");
 #endif
 
     printf("%-40s", "Testing maskmovq %mm4,%mm4...");
@@ -2812,6 +3188,32 @@ int main(int argc, char **argv)
             goto fail;
         printf("okay\n");
     }
+    else
+        printf("skipped\n");
+
+    printf("%-40s", "Testing vmovntdqa 64(%ecx),%zmm4...");
+    if ( stack_exec && cpu_has_avx512f )
+    {
+        decl_insn(evex_vmovntdqa);
+
+        asm volatile ( "vpxor %%xmm4, %%xmm4, %%xmm4\n"
+                       put_insn(evex_vmovntdqa, "vmovntdqa 64(%0), %%zmm4")
+                       :: "c" (NULL) );
+
+        set_insn(evex_vmovntdqa);
+        memset(res, 0x55, 192);
+        memset(res + 16, 0xff, 64);
+        regs.ecx = (unsigned long)res;
+        rc = x86_emulate(&ctxt, &emulops);
+        if ( rc != X86EMUL_OKAY || !check_eip(evex_vmovntdqa) )
+            goto fail;
+        asm ( "vpbroadcastd %1, %%zmm2\n\t"
+              "vpcmpeqd %%zmm4, %%zmm2, %%k0\n\t"
+              "kmovw %%k0, %0" : "=r" (rc) : "0" (~0) );
+        if ( rc != 0xffff )
+            goto fail;
+        printf("okay\n");
+    }
     else
         printf("skipped\n");
 
--- a/tools/tests/x86_emulator/x86-emulate.c
+++ b/tools/tests/x86_emulator/x86-emulate.c
@@ -210,6 +210,7 @@ int emul_test_get_fpu(
         if ( cpu_has_avx )
             break;
     case X86EMUL_FPU_opmask:
+    case X86EMUL_FPU_zmm:
         if ( cpu_has_avx512f )
             break;
     default:
--- a/tools/tests/x86_emulator/x86-emulate.h
+++ b/tools/tests/x86_emulator/x86-emulate.h
@@ -266,6 +266,16 @@ static inline uint64_t xgetbv(uint32_t x
     (res.b & (1U << 30)) != 0; \
 })
 
+#define cpu_has_avx512vl ({ \
+    struct cpuid_leaf res; \
+    emul_test_cpuid(1, 0, &res, NULL); \
+    if ( !(res.c & (1U << 27)) || ((xgetbv(0) & 0xe6) != 0xe6) ) \
+        res.b = 0; \
+    else \
+        emul_test_cpuid(7, 0, &res, NULL); \
+    (res.b & (1U << 31)) != 0; \
+})
+
 int emul_test_cpuid(
     uint32_t leaf,
     uint32_t subleaf,
--- a/xen/arch/x86/x86_emulate/x86_emulate.c
+++ b/xen/arch/x86/x86_emulate/x86_emulate.c
@@ -243,9 +243,27 @@ enum simd_opsize {
 };
 typedef uint8_t simd_opsize_t;
 
+enum disp8scale {
+    /* Values 0 ... 4 are explicit sizes. */
+    d8s_bw = 5,
+    d8s_dq,
+    /* EVEX.W ignored outside of 64-bit mode */
+    d8s_dq64,
+    /*
+     * All further values must strictly be last and in the order
+     * given so that arithmetic on the values works.
+     */
+    d8s_vl,
+    d8s_vl_by_2,
+    d8s_vl_by_4,
+    d8s_vl_by_8,
+};
+typedef uint8_t disp8scale_t;
+
 static const struct twobyte_table {
     opcode_desc_t desc;
-    simd_opsize_t size;
+    simd_opsize_t size:4;
+    disp8scale_t d8s:4;
 } twobyte_table[256] = {
     [0x00] = { ModRM },
     [0x01] = { ImplicitOps|ModRM },
@@ -260,8 +278,8 @@ static const struct twobyte_table {
     [0x0d] = { ImplicitOps|ModRM },
     [0x0e] = { ImplicitOps },
     [0x0f] = { ModRM|SrcImmByte },
-    [0x10] = { DstImplicit|SrcMem|ModRM|Mov, simd_any_fp },
-    [0x11] = { DstMem|SrcImplicit|ModRM|Mov, simd_any_fp },
+    [0x10] = { DstImplicit|SrcMem|ModRM|Mov, simd_any_fp, d8s_vl },
+    [0x11] = { DstMem|SrcImplicit|ModRM|Mov, simd_any_fp, d8s_vl },
     [0x12] = { DstImplicit|SrcMem|ModRM|Mov, simd_other },
     [0x13] = { DstMem|SrcImplicit|ModRM|Mov, simd_other },
     [0x14 ... 0x15] = { DstImplicit|SrcMem|ModRM, simd_packed_fp },
@@ -270,10 +288,10 @@ static const struct twobyte_table {
     [0x18 ... 0x1f] = { ImplicitOps|ModRM },
     [0x20 ... 0x21] = { DstMem|SrcImplicit|ModRM },
     [0x22 ... 0x23] = { DstImplicit|SrcMem|ModRM },
-    [0x28] = { DstImplicit|SrcMem|ModRM|Mov, simd_packed_fp },
-    [0x29] = { DstMem|SrcImplicit|ModRM|Mov, simd_packed_fp },
+    [0x28] = { DstImplicit|SrcMem|ModRM|Mov, simd_packed_fp, d8s_vl },
+    [0x29] = { DstMem|SrcImplicit|ModRM|Mov, simd_packed_fp, d8s_vl },
     [0x2a] = { DstImplicit|SrcMem|ModRM|Mov, simd_other },
-    [0x2b] = { DstMem|SrcImplicit|ModRM|Mov, simd_any_fp },
+    [0x2b] = { DstMem|SrcImplicit|ModRM|Mov, simd_any_fp, d8s_vl },
     [0x2c ... 0x2d] = { DstImplicit|SrcMem|ModRM|Mov, simd_other },
     [0x2e ... 0x2f] = { ImplicitOps|ModRM|TwoOp },
     [0x30 ... 0x35] = { ImplicitOps },
@@ -292,8 +310,8 @@ static const struct twobyte_table {
     [0x63 ... 0x67] = { DstImplicit|SrcMem|ModRM, simd_packed_int },
     [0x68 ... 0x6a] = { DstImplicit|SrcMem|ModRM, simd_other },
     [0x6b ... 0x6d] = { DstImplicit|SrcMem|ModRM, simd_packed_int },
-    [0x6e] = { DstImplicit|SrcMem|ModRM|Mov },
-    [0x6f] = { DstImplicit|SrcMem|ModRM|Mov, simd_packed_int },
+    [0x6e] = { DstImplicit|SrcMem|ModRM|Mov, simd_none, d8s_dq64 },
+    [0x6f] = { DstImplicit|SrcMem|ModRM|Mov, simd_packed_int, d8s_vl },
     [0x70] = { SrcImmByte|ModRM|TwoOp, simd_other },
     [0x71 ... 0x73] = { DstImplicit|SrcImmByte|ModRM },
     [0x74 ... 0x76] = { DstImplicit|SrcMem|ModRM, simd_packed_int },
@@ -301,8 +319,8 @@ static const struct twobyte_table {
     [0x78] = { ImplicitOps|ModRM },
     [0x79] = { DstReg|SrcMem|ModRM, simd_packed_int },
     [0x7c ... 0x7d] = { DstImplicit|SrcMem|ModRM, simd_other },
-    [0x7e] = { DstMem|SrcImplicit|ModRM|Mov },
-    [0x7f] = { DstMem|SrcImplicit|ModRM|Mov, simd_packed_int },
+    [0x7e] = { DstMem|SrcImplicit|ModRM|Mov, simd_none, d8s_dq64 },
+    [0x7f] = { DstMem|SrcImplicit|ModRM|Mov, simd_packed_int, d8s_vl },
     [0x80 ... 0x8f] = { DstImplicit|SrcImm },
     [0x90 ... 0x9f] = { ByteOp|DstMem|SrcNone|ModRM|Mov },
     [0xa0 ... 0xa1] = { ImplicitOps|Mov },
@@ -344,14 +362,14 @@ static const struct twobyte_table {
     [0xd0] = { DstImplicit|SrcMem|ModRM, simd_other },
     [0xd1 ... 0xd3] = { DstImplicit|SrcMem|ModRM, simd_other },
     [0xd4 ... 0xd5] = { DstImplicit|SrcMem|ModRM, simd_packed_int },
-    [0xd6] = { DstMem|SrcImplicit|ModRM|Mov, simd_other },
+    [0xd6] = { DstMem|SrcImplicit|ModRM|Mov, simd_other, 3 },
     [0xd7] = { DstReg|SrcImplicit|ModRM|Mov },
     [0xd8 ... 0xdf] = { DstImplicit|SrcMem|ModRM, simd_packed_int },
     [0xe0] = { DstImplicit|SrcMem|ModRM, simd_packed_int },
     [0xe1 ... 0xe2] = { DstImplicit|SrcMem|ModRM, simd_other },
     [0xe3 ... 0xe5] = { DstImplicit|SrcMem|ModRM, simd_packed_int },
     [0xe6] = { DstImplicit|SrcMem|ModRM|Mov, simd_other },
-    [0xe7] = { DstMem|SrcImplicit|ModRM|Mov, simd_packed_int },
+    [0xe7] = { DstMem|SrcImplicit|ModRM|Mov, simd_packed_int, d8s_vl },
     [0xe8 ... 0xef] = { DstImplicit|SrcMem|ModRM, simd_packed_int },
     [0xf0] = { DstImplicit|SrcMem|ModRM|Mov, simd_other },
     [0xf1 ... 0xf3] = { DstImplicit|SrcMem|ModRM, simd_other },
@@ -406,6 +424,7 @@ static const struct ext0f38_table {
     uint8_t to_mem:1;
     uint8_t two_op:1;
     uint8_t vsib:1;
+    disp8scale_t d8s:4;
 } ext0f38_table[256] = {
     [0x00 ... 0x0b] = { .simd_size = simd_packed_int },
     [0x0c ... 0x0f] = { .simd_size = simd_packed_fp },
@@ -418,7 +437,7 @@ static const struct ext0f38_table {
     [0x1c ... 0x1e] = { .simd_size = simd_packed_int, .two_op = 1 },
     [0x20 ... 0x25] = { .simd_size = simd_other, .two_op = 1 },
     [0x28 ... 0x29] = { .simd_size = simd_packed_int },
-    [0x2a] = { .simd_size = simd_packed_int, .two_op = 1 },
+    [0x2a] = { .simd_size = simd_packed_int, .two_op = 1, .d8s = d8s_vl },
     [0x2b] = { .simd_size = simd_packed_int },
     [0x2c ... 0x2d] = { .simd_size = simd_other },
     [0x2e ... 0x2f] = { .simd_size = simd_other, .to_mem = 1 },
@@ -656,6 +675,22 @@ union evex {
     };
 };
 
+#define EVEX_PFX_BYTES 4
+#define init_evex(stub) ({ \
+    uint8_t *buf_ = get_stub(stub); \
+    buf_[0] = 0x62; \
+    buf_ + EVEX_PFX_BYTES; \
+})
+
+#define copy_EVEX(ptr, evex) ({ \
+    if ( !mode_64bit() ) \
+        (evex).reg |= 8; \
+    (ptr)[1 - EVEX_PFX_BYTES] = (evex).raw[0]; \
+    (ptr)[2 - EVEX_PFX_BYTES] = (evex).raw[1]; \
+    (ptr)[3 - EVEX_PFX_BYTES] = (evex).raw[2]; \
+    container_of((ptr) + 1 - EVEX_PFX_BYTES, typeof(evex), raw[0]); \
+})
+
 #define rep_prefix()   (vex.pfx >= vex_f3)
 #define repe_prefix()  (vex.pfx == vex_f3)
 #define repne_prefix() (vex.pfx == vex_f2)
@@ -768,6 +803,7 @@ typedef union {
     uint64_t mmx;
     uint64_t __attribute__ ((aligned(16))) xmm[2];
     uint64_t __attribute__ ((aligned(32))) ymm[4];
+    uint64_t __attribute__ ((aligned(64))) zmm[8];
 } mmval_t;
 
 /*
@@ -1183,6 +1219,11 @@ static int _get_fpu(
 
     switch ( type )
     {
+    case X86EMUL_FPU_zmm:
+        if ( !(xcr0 & X86_XCR0_ZMM) || !(xcr0 & X86_XCR0_HI_ZMM) ||
+             !(xcr0 & X86_XCR0_OPMASK) )
+            return X86EMUL_UNHANDLEABLE;
+        /* fall through */
     case X86EMUL_FPU_ymm:
         if ( !(xcr0 & X86_XCR0_SSE) || !(xcr0 & X86_XCR0_YMM) )
             return X86EMUL_UNHANDLEABLE;
@@ -1777,6 +1818,7 @@ static bool vcpu_has(
 #define vcpu_has_clwb()        vcpu_has(         7, EBX, 24, ctxt, ops)
 #define vcpu_has_sha()         vcpu_has(         7, EBX, 29, ctxt, ops)
 #define vcpu_has_avx512bw()    vcpu_has(         7, EBX, 30, ctxt, ops)
+#define vcpu_has_avx512vl()    vcpu_has(         7, EBX, 31, ctxt, ops)
 #define vcpu_has_rdpid()       vcpu_has(         7, ECX, 22, ctxt, ops)
 #define vcpu_has_clzero()      vcpu_has(0x80000008, EBX,  0, ctxt, ops)
 
@@ -2150,6 +2192,65 @@ static unsigned long *decode_vex_gpr(
     return decode_gpr(regs, ~vex_reg & (mode_64bit() ? 0xf : 7));
 }
 
+static unsigned int decode_disp8scale(enum disp8scale scale,
+                                      const struct x86_emulate_state *state)
+{
+    switch ( scale )
+    {
+    case d8s_bw:
+        return state->evex.w;
+
+    default:
+        if ( scale < d8s_vl )
+            return scale;
+        if ( state->evex.br )
+        {
+    case d8s_dq:
+            return 2 + state->evex.w;
+        }
+        break;
+
+    case d8s_dq64:
+        return 2 + (state->op_bytes == 8);
+    }
+
+    switch ( state->simd_size )
+    {
+    case simd_any_fp:
+    case simd_single_fp:
+        if ( !(state->evex.pfx & VEX_PREFIX_SCALAR_MASK) )
+            break;
+        /* fall through */
+    case simd_scalar_opc:
+    case simd_scalar_vexw:
+        return 2 + state->evex.w;
+
+    case simd_128:
+        /* These should have an explicit size specified. */
+        ASSERT_UNREACHABLE();
+        return 4;
+
+    default:
+        break;
+    }
+
+    return 4 + state->evex.lr - (scale - d8s_vl);
+}
+
+#define avx512_vlen_check(lig) do { \
+    switch ( evex.lr ) \
+    { \
+    default: \
+        generate_exception(EXC_UD); \
+    case 2: \
+        break; \
+    case 0: case 1: \
+        if (!(lig)) \
+            host_and_vcpu_must_have(avx512vl); \
+        break; \
+    } \
+} while ( false )
+
 static bool is_aligned(enum x86_segment seg, unsigned long offs,
                        unsigned int size, struct x86_emulate_ctxt *ctxt,
                        const struct x86_emulate_ops *ops)
@@ -2399,6 +2500,7 @@ x86_decode_twobyte(
         if ( vex.pfx == vex_f3 ) /* movq xmm/m64,xmm */
         {
     case X86EMUL_OPC_VEX_F3(0, 0x7e): /* vmovq xmm/m64,xmm */
+    case X86EMUL_OPC_EVEX_F3(0, 0x7e): /* vmovq xmm/m64,xmm */
             state->desc = DstImplicit | SrcMem | TwoOp;
             state->simd_size = simd_other;
             /* Avoid the state->desc clobbering of TwoOp below. */
@@ -2469,7 +2571,7 @@ x86_decode_twobyte(
     }
 
     /*
-     * Scalar forms of most VEX-encoded TwoOp instructions have
+     * Scalar forms of most VEX-/EVEX-encoded TwoOp instructions have
      * three operands.  Those which do really have two operands
      * should have exited earlier.
      */
@@ -2834,6 +2936,8 @@ x86_decode(
 
     if ( d & ModRM )
     {
+        unsigned int disp8scale = 0;
+
         d &= ~ModRM;
 #undef ModRM /* Only its aliases are valid to use from here on. */
         modrm_reg = ((rex_prefix & 4) << 1) | ((modrm & 0x38) >> 3);
@@ -2876,6 +2980,9 @@ x86_decode(
             break;
 
         case ext_0f:
+            if ( evex_encoded() )
+                disp8scale = decode_disp8scale(twobyte_table[b].d8s, state);
+
             switch ( b )
             {
             case 0x20: /* mov cr,reg */
@@ -2889,6 +2996,11 @@ x86_decode(
                  */
                 modrm_mod = 3;
                 break;
+
+            case 0x7e: /* vmovq xmm/m64,xmm needs special casing */
+                if ( disp8scale == 2 && evex.pfx == vex_f3 )
+                    disp8scale = 3;
+                break;
             }
             break;
 
@@ -2900,6 +3012,8 @@ x86_decode(
             if ( ext0f38_table[b].vsib )
                 d |= vSIB;
             state->simd_size = ext0f38_table[b].simd_size;
+            if ( evex_encoded() )
+                disp8scale = decode_disp8scale(ext0f38_table[b].d8s, state);
             break;
 
         case ext_8f09:
@@ -2968,7 +3082,7 @@ x86_decode(
                     ea.mem.off = insn_fetch_type(int16_t);
                 break;
             case 1:
-                ea.mem.off += insn_fetch_type(int8_t);
+                ea.mem.off += insn_fetch_type(int8_t) << disp8scale;
                 break;
             case 2:
                 ea.mem.off += insn_fetch_type(int16_t);
@@ -3027,7 +3141,7 @@ x86_decode(
                 pc_rel = mode_64bit();
                 break;
             case 1:
-                ea.mem.off += insn_fetch_type(int8_t);
+                ea.mem.off += insn_fetch_type(int8_t) << disp8scale;
                 break;
             case 2:
                 ea.mem.off += insn_fetch_type(int32_t);
@@ -3228,10 +3342,11 @@ x86_emulate(
     struct x86_emulate_state state;
     int rc;
     uint8_t b, d, *opc = NULL;
-    unsigned int first_byte = 0, insn_bytes = 0;
+    unsigned int first_byte = 0, elem_bytes, insn_bytes = 0;
+    uint64_t op_mask = ~0ULL;
     bool singlestep = (_regs.eflags & X86_EFLAGS_TF) &&
 	    !is_branch_step(ctxt, ops);
-    bool sfence = false;
+    bool sfence = false, fault_suppression = false;
     struct operand src = { .reg = PTR_POISON };
     struct operand dst = { .reg = PTR_POISON };
     unsigned long cr4;
@@ -3272,6 +3387,7 @@ x86_emulate(
     b = ctxt->opcode;
     d = state.desc;
 #define state (&state)
+    elem_bytes = 4 << evex.w;
 
     generate_exception_if(state->not_64bit && mode_64bit(), EXC_UD);
 
@@ -3346,6 +3462,28 @@ x86_emulate(
         break;
     }
 
+    /* With a memory operand, fetch the mask register in use (if any). */
+    if ( ea.type == OP_MEM && evex.opmsk )
+    {
+        uint8_t *stb = get_stub(stub);
+
+        /* KMOV{W,Q} %k<n>, (%rax) */
+        stb[0] = 0xc4;
+        stb[1] = 0xe1;
+        stb[2] = cpu_has_avx512bw ? 0xf8 : 0x78;
+        stb[3] = 0x91;
+        stb[4] = evex.opmsk << 3;
+        insn_bytes = 5;
+        stb[5] = 0xc3;
+
+        invoke_stub("", "", "+m" (op_mask) : "a" (&op_mask));
+
+        insn_bytes = 0;
+        put_stub(stub);
+
+        fault_suppression = true;
+    }
+
     /* Decode (but don't fetch) the destination operand: register or memory. */
     switch ( d & DstMask )
     {
@@ -5708,6 +5846,41 @@ x86_emulate(
         insn_bytes = PFX_BYTES + 2;
         break;
 
+    CASE_SIMD_PACKED_FP(_EVEX, 0x0f, 0x2b): /* vmovntp{s,d} [xyz]mm,mem */
+        generate_exception_if(ea.type != OP_MEM || evex.opmsk, EXC_UD);
+        sfence = true;
+        fault_suppression = false;
+        /* fall through */
+    CASE_SIMD_PACKED_FP(_EVEX, 0x0f, 0x10): /* vmovup{s,d} [xyz]mm/mem,[xyz]mm{k} */
+    CASE_SIMD_SCALAR_FP(_EVEX, 0x0f, 0x10): /* vmovs{s,d} mem,xmm{k} */
+                                            /* vmovs{s,d} xmm,xmm,xmm{k} */
+    CASE_SIMD_PACKED_FP(_EVEX, 0x0f, 0x11): /* vmovup{s,d} [xyz]mm,[xyz]mm/mem{k} */
+    CASE_SIMD_SCALAR_FP(_EVEX, 0x0f, 0x11): /* vmovs{s,d} xmm,mem{k} */
+                                            /* vmovs{s,d} xmm,xmm,xmm{k} */
+    CASE_SIMD_PACKED_FP(_EVEX, 0x0f, 0x28): /* vmovap{s,d} [xyz]mm/mem,[xyz]mm{k} */
+    CASE_SIMD_PACKED_FP(_EVEX, 0x0f, 0x29): /* vmovap{s,d} [xyz]mm,[xyz]mm/mem{k} */
+        /* vmovs{s,d} to/from memory have only two operands. */
+        if ( (b & ~1) == 0x10 && ea.type == OP_MEM )
+            d |= TwoOp;
+        generate_exception_if(evex.br, EXC_UD);
+        generate_exception_if(evex.w != (evex.pfx & VEX_PREFIX_DOUBLE_MASK),
+                              EXC_UD);
+        host_and_vcpu_must_have(avx512f);
+        avx512_vlen_check(evex.pfx & VEX_PREFIX_SCALAR_MASK);
+    simd_zmm:
+        get_fpu(X86EMUL_FPU_zmm);
+        opc = init_evex(stub);
+        opc[0] = b;
+        opc[1] = modrm;
+        if ( ea.type == OP_MEM )
+        {
+            /* convert memory operand to (%rAX) */
+            evex.b = 1;
+            opc[1] &= 0x38;
+        }
+        insn_bytes = EVEX_PFX_BYTES + 2;
+        break;
+
     case X86EMUL_OPC_66(0x0f, 0x12):       /* movlpd m64,xmm */
     case X86EMUL_OPC_VEX_66(0x0f, 0x12):   /* vmovlpd m64,xmm,xmm */
     CASE_SIMD_PACKED_FP(, 0x0f, 0x13):     /* movlp{s,d} xmm,m64 */
@@ -6348,6 +6521,41 @@ x86_emulate(
         ASSERT(!state->simd_size);
         break;
 
+    case X86EMUL_OPC_EVEX_66(0x0f, 0x6e): /* vmov{d,q} r/m,xmm */
+    case X86EMUL_OPC_EVEX_66(0x0f, 0x7e): /* vmov{d,q} xmm,r/m */
+        generate_exception_if((evex.lr || evex.opmsk || evex.br ||
+                               evex.reg != 0xf || !evex.RX),
+                              EXC_UD);
+        host_and_vcpu_must_have(avx512f);
+        get_fpu(X86EMUL_FPU_zmm);
+
+        opc = init_evex(stub);
+        opc[0] = b;
+        /* Convert memory/GPR operand to (%rAX). */
+        evex.b = 1;
+        if ( !mode_64bit() )
+            evex.w = 0;
+        opc[1] = modrm & 0x38;
+        insn_bytes = EVEX_PFX_BYTES + 2;
+        opc[2] = 0xc3;
+
+        copy_EVEX(opc, evex);
+        invoke_stub("", "", "+m" (src.val) : "a" (&src.val));
+        dst.val = src.val;
+
+        put_stub(stub);
+        ASSERT(!state->simd_size);
+        break;
+
+    case X86EMUL_OPC_EVEX_F3(0x0f, 0x7e): /* vmovq xmm/m64,xmm */
+    case X86EMUL_OPC_EVEX_66(0x0f, 0xd6): /* vmovq xmm,xmm/m64 */
+        generate_exception_if(evex.lr || !evex.w || evex.opmsk || evex.br,
+                              EXC_UD);
+        host_and_vcpu_must_have(avx512f);
+        d |= TwoOp;
+        op_bytes = 8;
+        goto simd_zmm;
+
     case X86EMUL_OPC_66(0x0f, 0xe7):     /* movntdq xmm,m128 */
     case X86EMUL_OPC_VEX_66(0x0f, 0xe7): /* vmovntdq {x,y}mm,mem */
         generate_exception_if(ea.type != OP_MEM, EXC_UD);
@@ -6368,6 +6576,30 @@ x86_emulate(
             goto simd_0f_avx;
         goto simd_0f_sse2;
 
+    case X86EMUL_OPC_EVEX_66(0x0f, 0xe7): /* vmovntdq [xyz]mm,mem */
+        generate_exception_if(ea.type != OP_MEM || evex.opmsk || evex.w,
+                              EXC_UD);
+        sfence = true;
+        fault_suppression = false;
+        /* fall through */
+    case X86EMUL_OPC_EVEX_66(0x0f, 0x6f): /* vmovdqa{32,64} [xyz]mm/mem,[xyz]mm{k} */
+    case X86EMUL_OPC_EVEX_F3(0x0f, 0x6f): /* vmovdqu{32,64} [xyz]mm/mem,[xyz]mm{k} */
+    case X86EMUL_OPC_EVEX_66(0x0f, 0x7f): /* vmovdqa{32,64} [xyz]mm,[xyz]mm/mem{k} */
+    case X86EMUL_OPC_EVEX_F3(0x0f, 0x7f): /* vmovdqu{32,64} [xyz]mm,[xyz]mm/mem{k} */
+    vmovdqa:
+        generate_exception_if(evex.br, EXC_UD);
+        host_and_vcpu_must_have(avx512f);
+        avx512_vlen_check(false);
+        d |= TwoOp;
+        op_bytes = 16 << evex.lr;
+        goto simd_zmm;
+
+    case X86EMUL_OPC_EVEX_F2(0x0f, 0x6f): /* vmovdqu{8,16} [xyz]mm/mem,[xyz]mm{k} */
+    case X86EMUL_OPC_EVEX_F2(0x0f, 0x7f): /* vmovdqu{8,16} [xyz]mm,[xyz]mm/mem{k} */
+        host_and_vcpu_must_have(avx512bw);
+        elem_bytes = 1 << evex.w;
+        goto vmovdqa;
+
     case X86EMUL_OPC_VEX_66(0x0f, 0xd6): /* vmovq xmm,xmm/m64 */
         generate_exception_if(vex.l, EXC_UD);
         d |= TwoOp;
@@ -7734,6 +7966,15 @@ x86_emulate(
         }
         goto movdqa;
 
+    case X86EMUL_OPC_EVEX_66(0x0f38, 0x2a): /* vmovntdqa mem,[xyz]mm */
+        generate_exception_if(ea.type != OP_MEM || evex.opmsk || evex.w,
+                              EXC_UD);
+        /* Ignore the non-temporal hint for now, using vmovdqa32 instead. */
+        asm volatile ( "mfence" ::: "memory" );
+        b = 0x6f;
+        evex.opcx = vex_0f;
+        goto vmovdqa;
+
     case X86EMUL_OPC_VEX_66(0x0f38, 0x2c): /* vmaskmovps mem,{x,y}mm,{x,y}mm */
     case X86EMUL_OPC_VEX_66(0x0f38, 0x2d): /* vmaskmovpd mem,{x,y}mm,{x,y}mm */
     case X86EMUL_OPC_VEX_66(0x0f38, 0x2e): /* vmaskmovps {x,y}mm,{x,y}mm,mem */
@@ -8787,17 +9028,27 @@ x86_emulate(
     else if ( state->simd_size )
     {
         generate_exception_if(!op_bytes, EXC_UD);
-        generate_exception_if(vex.opcx && (d & TwoOp) && vex.reg != 0xf,
+        generate_exception_if((vex.opcx && (d & TwoOp) &&
+                               (vex.reg != 0xf || (evex_encoded() && !evex.RX))),
                               EXC_UD);
 
         if ( !opc )
             BUG();
-        opc[insn_bytes - PFX_BYTES] = 0xc3;
-        copy_REX_VEX(opc, rex_prefix, vex);
+        if ( evex_encoded() )
+        {
+            opc[insn_bytes - EVEX_PFX_BYTES] = 0xc3;
+            copy_EVEX(opc, evex);
+        }
+        else
+        {
+            opc[insn_bytes - PFX_BYTES] = 0xc3;
+            copy_REX_VEX(opc, rex_prefix, vex);
+        }
 
         if ( ea.type == OP_MEM )
         {
             uint32_t mxcsr = 0;
+            uint64_t full = 0;
 
             if ( op_bytes < 16 ||
                  (vex.opcx
@@ -8819,6 +9070,44 @@ x86_emulate(
                                   !is_aligned(ea.mem.seg, ea.mem.off, op_bytes,
                                               ctxt, ops),
                                   EXC_GP, 0);
+
+            if ( evex.br )
+            {
+                ASSERT((d & DstMask) != DstMem);
+                op_bytes = elem_bytes;
+            }
+            if ( evex.opmsk )
+            {
+                ASSERT(!(op_bytes % elem_bytes));
+                full = ~0ULL >> (64 - op_bytes / elem_bytes);
+                op_mask &= full;
+            }
+            if ( fault_suppression )
+            {
+                if ( !op_mask )
+                    goto simd_no_mem;
+                if ( !evex.br )
+                {
+                    first_byte = __builtin_ctzll(op_mask);
+                    op_mask >>= first_byte;
+                    full >>= first_byte;
+                    first_byte *= elem_bytes;
+                    op_bytes = (64 - __builtin_clzll(op_mask)) * elem_bytes;
+                }
+            }
+            /*
+             * Independent of fault suppression we may need to read (parts of)
+             * the memory operand for the purpose of merging without splitting
+             * the write below into multiple ones. Note that the EVEX.Z check
+             * here isn't strictly needed, due to there not currently being
+             * any instructions allowing zeroing-merging on memory writes (and
+             * we raise #UD during DstMem processing far above in this case),
+             * yet conceptually the read is then unnecessary.
+             */
+            if ( evex.opmsk && !evex.z && (d & DstMask) == DstMem &&
+                 op_mask != full )
+                d = (d & ~SrcMask) | SrcMem;
+
             switch ( d & SrcMask )
             {
             case SrcMem:
@@ -8865,7 +9154,10 @@ x86_emulate(
             }
         }
         else
+        {
+        simd_no_mem:
             dst.type = OP_NONE;
+        }
 
         /* {,v}maskmov{q,dqu}, as an exception, uses rDI. */
         if ( likely((ctxt->opcode & ~(X86EMUL_OPC_PFX_MASK |
--- a/xen/arch/x86/x86_emulate/x86_emulate.h
+++ b/xen/arch/x86/x86_emulate/x86_emulate.h
@@ -171,6 +171,7 @@ enum x86_emulate_fpu_type {
     X86EMUL_FPU_xmm, /* SSE instruction set (%xmm0-%xmm7/15) */
     X86EMUL_FPU_ymm, /* AVX/XOP instruction set (%ymm0-%ymm7/15) */
     X86EMUL_FPU_opmask, /* AVX512 opmask instruction set (%k0-%k7) */
+    X86EMUL_FPU_zmm, /* AVX512 instruction set (%zmm0-%zmm7/31) */
     /* This sentinel will never be passed to ->get_fpu(). */
     X86EMUL_FPU_none
 };
--- a/xen/include/asm-x86/cpufeature.h
+++ b/xen/include/asm-x86/cpufeature.h
@@ -105,6 +105,7 @@
 #define cpu_has_smap            boot_cpu_has(X86_FEATURE_SMAP)
 #define cpu_has_sha             boot_cpu_has(X86_FEATURE_SHA)
 #define cpu_has_avx512bw        boot_cpu_has(X86_FEATURE_AVX512BW)
+#define cpu_has_avx512vl        boot_cpu_has(X86_FEATURE_AVX512VL)
 
 /* CPUID level 0x80000007.edx */
 #define cpu_has_itsc            boot_cpu_has(X86_FEATURE_ITSC)




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  parent reply index

Thread overview: 465+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-08-09  8:15 [PATCH 0/6] x86emul: fixes, improvements, and beginnings of AVX512 support Jan Beulich
2018-08-09  8:23 ` [PATCH 1/6] x86emul: fix FMA scalar operand sizes Jan Beulich
2018-08-09  8:24 ` [PATCH 2/6] x86emul: extend MASKMOV{Q,DQU} tests Jan Beulich
2018-08-09  8:24 ` [PATCH 3/6] x86emul: support AVX512 opmask insns Jan Beulich
2018-08-09  8:25 ` [PATCH 4/6] x86emul: clean up AVX2 insn use in test harness Jan Beulich
2018-08-09  8:25 ` [PATCH 5/6] x86emul: correct EVEX decoding Jan Beulich
2018-08-09  8:26 ` [PATCH 6/6] x86emul: generalize vector length handling for AVX512/EVEX Jan Beulich
2018-08-29 14:20 ` [PATCH v2 0/6] x86emul: fixes, improvements, and beginnings of AVX512 support Jan Beulich
2018-08-29 14:23   ` [PATCH v2 1/6] x86emul: fix FMA scalar operand sizes Jan Beulich
2018-09-03 16:43     ` Andrew Cooper
2018-09-04  7:52       ` Jan Beulich
2018-08-29 14:23   ` [PATCH v2 2/6] x86emul: extend MASKMOV{Q,DQU} tests Jan Beulich
2018-09-03 16:44     ` [PATCH v2 2/6] x86emul: extend MASKMOV{Q, DQU} tests Andrew Cooper
2018-08-29 14:24   ` [PATCH v2 3/6] x86emul: support AVX512 opmask insns Jan Beulich
2018-09-03 17:57     ` Andrew Cooper
2018-09-04  7:58       ` Jan Beulich
2018-08-29 14:24   ` [PATCH v2 4/6] x86emul: clean up AVX2 insn use in test harness Jan Beulich
2018-09-03 18:04     ` Andrew Cooper
2018-08-29 14:25   ` [PATCH v2 5/6] x86emul: correct EVEX decoding Jan Beulich
2018-09-04 10:48     ` Andrew Cooper
2018-09-04 12:48       ` Jan Beulich
2018-08-29 14:25   ` [PATCH v2 6/6] x86emul: generalize vector length handling for AVX512/EVEX Jan Beulich
2018-09-04 11:02     ` Andrew Cooper
2018-09-04 12:50       ` Jan Beulich
2018-09-18 11:46 ` [PATCH v3 00/34] x86emul: fixes, improvements, and beginnings of AVX512 support Jan Beulich
2018-09-18 11:53   ` [PATCH v3 01/34] x86emul: support AVX512 opmask insns Jan Beulich
2018-10-25 18:32     ` Andrew Cooper
2018-10-26  9:03       ` Jan Beulich
2018-10-26 11:29         ` Andrew Cooper
2018-10-26 11:59           ` Jan Beulich
2018-10-26 12:19             ` Andrew Cooper
2018-10-26 12:34               ` Jan Beulich
2018-09-18 11:53   ` [PATCH v3 02/34] x86/HVM: grow MMIO cache data size to 64 bytes Jan Beulich
2018-09-18 16:05     ` Paul Durrant
2018-10-25 18:36     ` Andrew Cooper
2018-10-26  9:04       ` Jan Beulich
2018-10-26 11:29         ` Andrew Cooper
2018-09-18 11:55   ` [PATCH v3 03/34] x86emul: correct EVEX decoding Jan Beulich
2018-09-18 11:55   ` [PATCH v3 04/34] x86emul: generalize vector length handling for AVX512/EVEX Jan Beulich
2018-09-18 11:56   ` [PATCH v3 05/34] x86emul: support basic AVX512 moves Jan Beulich
2018-09-18 11:57   ` [PATCH v3 06/34] x86emul: test for correct EVEX Disp8 scaling Jan Beulich
2018-09-18 11:57   ` [PATCH v3 07/34] x86emul: use AVX512 logic for emulating V{, P}MASKMOV* Jan Beulich
2018-09-18 11:58   ` [PATCH v3 08/34] x86emul: support AVX512F legacy-equivalent arithmetic FP insns Jan Beulich
2018-09-18 11:59   ` [PATCH v3 09/34] x86emul: support AVX512DQ logic " Jan Beulich
2018-09-18 11:59   ` [PATCH v3 10/34] x86emul: support AVX512F "normal" FP compare insns Jan Beulich
2018-09-18 12:00   ` [PATCH v3 11/34] x86emul: support AVX512F misc legacy-equivalent FP insns Jan Beulich
2018-09-18 12:00   ` [PATCH v3 12/34] x86emul: support AVX512F fused-multiply-add insns Jan Beulich
2018-09-18 12:01   ` [PATCH v3 13/34] x86emul: support AVX512F legacy-equivalent logic insns Jan Beulich
2018-09-18 12:02   ` [PATCH v3 14/34] x86emul: support AVX512{F, DQ} FP broadcast insns Jan Beulich
2018-09-18 12:03   ` [PATCH v3 15/34] x86emul: support AVX512F v{, u}comis{d, s} insns Jan Beulich
2018-09-18 12:03   ` [PATCH v3 16/34] x86emul/test: introduce eq() Jan Beulich
2018-09-18 12:04   ` [PATCH v3 17/34] x86emul: support AVX512{F, BW} packed integer compare insns Jan Beulich
2018-09-18 12:05   ` [PATCH v3 18/34] x86emul: support AVX512{F, BW} packed integer arithmetic insns Jan Beulich
2018-09-18 12:05   ` [PATCH v3 19/34] x86emul: use simd_128 also for legacy vector shift insns Jan Beulich
2018-09-18 12:05   ` [PATCH v3 20/34] x86emul: support AVX512{F, BW} shift/rotate insns Jan Beulich
2018-09-18 12:06   ` [PATCH v3 21/34] x86emul: support AVX512{F, BW, DQ} extract insns Jan Beulich
2018-09-18 12:07   ` [PATCH v3 22/34] x86emul: support AVX512{F, BW, DQ} insert insns Jan Beulich
2018-09-18 12:07   ` [PATCH v3 23/34] x86emul: basic AVX512F testing Jan Beulich
2018-09-18 12:08   ` [PATCH v3 24/34] x86emul: support AVX512{F, BW, DQ} integer broadcast insns Jan Beulich
2018-09-18 12:09   ` [PATCH v3 25/34] x86emul: basic AVX512VL testing Jan Beulich
2018-09-18 12:09   ` [PATCH v3 26/34] x86emul: support AVX512{F, BW} zero- and sign-extending moves Jan Beulich
2018-09-18 12:09   ` [PATCH v3 27/34] x86emul: support AVX512{F, BW} down conversion moves Jan Beulich
2018-09-18 12:10   ` [PATCH v3 28/34] x86emul: support AVX512{F, BW} integer unpack insns Jan Beulich
2018-09-18 12:11   ` [PATCH v3 29/34] x86emul: support AVX512{F, BW, _VBMI} full permute insns Jan Beulich
2018-09-18 12:11   ` [PATCH v3 29/34] x86emul: support AVX512{F, BW} integer shuffle insns Jan Beulich
2018-09-18 12:12   ` [PATCH v3 30/34] x86emul: support AVX512{BW, DQ} mask move insns Jan Beulich
2018-09-18 12:14   ` [PATCH v3 32/34] x86emul: basic AVX512BW testing Jan Beulich
2018-09-18 12:14   ` [PATCH v3 33/34] x86emul: basic AVX512DQ testing Jan Beulich
2018-09-18 12:14   ` [PATCH v3 34/34] x86emul: also allow running the 32-bit harness on a 64-bit distro Jan Beulich
2018-09-25 13:14 ` [PATCH v4 00/44] x86emul: fixes, improvements, and beginnings of AVX512 support Jan Beulich
2018-09-25 13:25   ` [PATCH v4 01/44] x86emul: support AVX512 opmask insns Jan Beulich
2018-09-26  6:06     ` Jan Beulich
2018-09-25 13:26   ` [PATCH v4 02/44] x86/HVM: grow MMIO cache data size to 64 bytes Jan Beulich
2018-09-25 13:27   ` [PATCH v4 03/44] x86emul: correct EVEX decoding Jan Beulich
2018-10-26 14:33     ` Andrew Cooper
2018-09-25 13:28   ` [PATCH v4 04/44] x86emul: generalize vector length handling for AVX512/EVEX Jan Beulich
2018-10-26 16:10     ` Andrew Cooper
2018-09-25 13:28   ` Jan Beulich [this message]
2018-11-13 17:12     ` [PATCH v4 05/44] x86emul: support basic AVX512 moves Andrew Cooper
2018-11-14 14:35       ` Jan Beulich
2018-11-14 16:26         ` Andrew Cooper
2018-11-15  9:54           ` Jan Beulich
2018-09-25 13:29   ` [PATCH v4 06/44] x86emul: test for correct EVEX Disp8 scaling Jan Beulich
2018-11-12 17:42     ` Andrew Cooper
2018-11-13 11:12       ` Jan Beulich
2018-11-13 15:45         ` Andrew Cooper
2018-11-14 14:17           ` Jan Beulich
2018-11-14 14:42             ` Andrew Cooper
2018-11-14 14:58               ` Jan Beulich
2018-09-25 13:29   ` [PATCH v4 07/44] x86emul: also allow running the 32-bit harness on a 64-bit distro Jan Beulich
2018-11-12 17:50     ` Andrew Cooper
2018-11-13 11:42       ` Jan Beulich
2018-11-13 15:58         ` Andrew Cooper
2018-11-14  8:42           ` Jan Beulich
2018-09-25 13:30   ` [PATCH v4 08/44] x86emul: use AVX512 logic for emulating V{, P}MASKMOV* Jan Beulich
2018-11-13 18:12     ` Andrew Cooper
2018-09-25 13:31   ` [PATCH v4 09/44] x86emul: support AVX512F legacy-equivalent arithmetic FP insns Jan Beulich
2018-11-13 18:21     ` Andrew Cooper
2018-09-25 13:32   ` [PATCH v4 10/44] x86emul: support AVX512DQ logic " Jan Beulich
2018-11-13 18:56     ` Andrew Cooper
2018-09-25 13:32   ` [PATCH v4 11/44] x86emul: support AVX512F "normal" FP compare insns Jan Beulich
2018-11-13 19:04     ` Andrew Cooper
2018-11-14 14:41       ` Jan Beulich
2018-11-14 14:45         ` Andrew Cooper
2018-09-25 13:33   ` [PATCH v4 12/44] x86emul: support AVX512F misc legacy-equivalent FP insns Jan Beulich
2018-11-13 19:17     ` Andrew Cooper
2018-09-25 13:33   ` [PATCH v4 13/44] x86emul: support AVX512F fused-multiply-add insns Jan Beulich
2018-11-13 19:28     ` Andrew Cooper
2018-09-25 13:34   ` [PATCH v4 14/44] x86emul: support AVX512F legacy-equivalent logic insns Jan Beulich
2018-11-13 19:30     ` Andrew Cooper
2018-09-25 13:35   ` [PATCH v4 15/44] x86emul: support AVX512{F, DQ} FP broadcast insns Jan Beulich
2018-11-13 19:37     ` Andrew Cooper
2018-09-25 13:35   ` [PATCH v4 16/44] x86emul: support AVX512F v{, u}comis{d, s} insns Jan Beulich
2018-11-13 19:39     ` Andrew Cooper
2018-09-25 13:36   ` [PATCH v4 17/44] x86emul/test: introduce eq() Jan Beulich
2018-10-26 11:31     ` Andrew Cooper
2018-09-25 13:37   ` [PATCH v4 18/44] x86emul: support AVX512{F, BW} packed integer compare insns Jan Beulich
2018-09-25 13:37   ` [PATCH v4 19/44] x86emul: support AVX512{F, BW} packed integer arithmetic insns Jan Beulich
2018-09-25 13:38   ` [PATCH v4 20/44] x86emul: use simd_128 also for legacy vector shift insns Jan Beulich
2018-09-25 13:39   ` [PATCH v4 21/44] x86emul: support AVX512{F, BW} shift/rotate insns Jan Beulich
2018-09-25 13:40   ` [PATCH v4 22/44] x86emul: support AVX512{F, BW, DQ} extract insns Jan Beulich
2018-09-25 13:40   ` [PATCH v4 23/44] x86emul: support AVX512{F, BW, DQ} insert insns Jan Beulich
2018-09-25 13:41   ` [PATCH v4 24/44] x86emul: basic AVX512F testing Jan Beulich
2018-09-25 13:41   ` [PATCH v4 25/44] x86emul: support AVX512{F, BW, DQ} integer broadcast insns Jan Beulich
2018-09-25 13:42   ` [PATCH v4 26/44] x86emul: basic AVX512VL testing Jan Beulich
2018-09-25 13:43   ` [PATCH v4 27/44] x86emul: support AVX512{F, BW} zero- and sign-extending moves Jan Beulich
2018-09-25 13:43   ` [PATCH v4 28/44] x86emul: support AVX512{F, BW} down conversion moves Jan Beulich
2018-09-25 13:44   ` [PATCH v4 29/44] x86emul: support AVX512{F, BW} integer unpack insns Jan Beulich
2018-09-25 13:44   ` [PATCH v4 30/44] x86emul: support AVX512{F, BW, _VBMI} full permute insns Jan Beulich
2018-09-25 13:46   ` [PATCH v4 31/44] x86emul: support AVX512{F, BW} integer shuffle insns Jan Beulich
2018-09-25 13:46   ` [PATCH v4 32/44] x86emul: support AVX512{BW, DQ} mask move insns Jan Beulich
2018-09-25 13:47   ` [PATCH v4 33/44] x86emul: basic AVX512BW testing Jan Beulich
2018-09-25 13:48   ` [PATCH v4 34/44] x86emul: basic AVX512DQ testing Jan Beulich
2018-09-25 13:48   ` [PATCH v4 35/44] x86emul: support AVX512F move high/low insns Jan Beulich
2018-09-25 13:49   ` [PATCH v4 36/44] x86emul: support AVX512F move duplicate insns Jan Beulich
2018-09-25 13:49   ` [PATCH v4 37/44] x86emul: support AVX512{F, BW, VBMI} permute insns Jan Beulich
2018-09-25 13:50   ` [PATCH v4 38/44] x86emul: support AVX512BW pack insns Jan Beulich
2018-09-25 13:51   ` [PATCH v4 39/44] x86emul: support AVX512F floating-point conversion insns Jan Beulich
2018-09-25 13:52   ` [PATCH v4 40/44] x86emul: support AVX512F legacy-equivalent packed int/FP " Jan Beulich
2018-09-25 13:53   ` [PATCH v4 41/44] x86emul: support AVX512F legacy-equivalent scalar " Jan Beulich
2018-09-25 13:53   ` [PATCH v4 42/44] x86emul: support AVX512DQ packed quad-int/FP " Jan Beulich
2018-09-25 13:54   ` [PATCH v4 43/44] x86emul: support AVX512{F, DQ} uint-to-FP " Jan Beulich
2018-09-25 13:55   ` [PATCH v4 44/44] x86emul: support AVX512{F, DQ} FP-to-uint " Jan Beulich
2018-11-19 10:00 ` [PATCH v5 00/47] x86emul: fair parts of AVX512 support Jan Beulich
2018-11-19 10:13   ` [PATCH v5 01/47] x86emul: introduce IMPOSSIBLE() Jan Beulich
2018-11-19 18:11     ` Andrew Cooper
2018-11-20  8:12       ` Jan Beulich
2018-11-19 10:13   ` [PATCH v5 02/47] x86emul: support basic AVX512 moves Jan Beulich
2018-11-19 18:35     ` Andrew Cooper
2018-11-19 10:14   ` [PATCH v5 03/47] x86emul: test for correct EVEX Disp8 scaling Jan Beulich
2018-11-19 18:35     ` Andrew Cooper
2018-11-19 10:14   ` [PATCH v5 04/47] x86emul: also allow running the 32-bit harness on a 64-bit distro Jan Beulich
2018-11-19 18:40     ` Andrew Cooper
2018-11-19 10:15   ` [PATCH v5 05/47] x86emul: use AVX512 logic for emulating V{, P}MASKMOV* Jan Beulich
2018-11-19 10:16   ` [PATCH v5 06/47] x86emul: support AVX512F legacy-equivalent arithmetic FP insns Jan Beulich
2018-11-19 10:16   ` [PATCH v5 07/47] x86emul: support AVX512DQ logic " Jan Beulich
2018-11-19 10:17   ` [PATCH v5 08/47] x86emul: support basic AVX512F FP compare insns Jan Beulich
2018-11-19 10:17   ` [PATCH v5 09/47] x86emul: support AVX512F misc legacy-equivalent FP insns Jan Beulich
2018-11-19 10:18   ` [PATCH v5 10/47] x86emul: support AVX512F fused-multiply-add insns Jan Beulich
2018-11-19 10:18   ` [PATCH v5 11/47] x86emul: support AVX512F legacy-equivalent logic insns Jan Beulich
2018-11-19 10:19   ` [PATCH v5 12/47] x86emul: support AVX512{F, DQ} FP broadcast insns Jan Beulich
2018-11-19 18:44     ` Andrew Cooper
2018-11-19 10:20   ` [PATCH v5 13/47] x86emul: support AVX512F v{, u}comis{d, s} insns Jan Beulich
2018-11-19 10:21   ` [PATCH v5 14/47] x86emul: support AVX512{F, BW} packed integer compare insns Jan Beulich
2018-11-19 19:09     ` Andrew Cooper
2018-11-19 10:21   ` [PATCH v5 15/47] x86emul: support AVX512{F, BW} packed integer arithmetic insns Jan Beulich
2018-11-19 19:18     ` Andrew Cooper
2018-11-19 10:22   ` [PATCH v5 16/47] x86emul: use simd_128 also for legacy vector shift insns Jan Beulich
2018-11-19 19:21     ` Andrew Cooper
2018-11-19 10:22   ` [PATCH v5 17/47] x86emul: support AVX512{F, BW} shift/rotate insns Jan Beulich
2018-11-19 10:23   ` [PATCH v5 18/47] x86emul: support AVX512{F, BW, DQ} extract insns Jan Beulich
2018-11-19 10:23   ` [PATCH v5 19/47] x86emul: support AVX512{F, BW, DQ} insert insns Jan Beulich
2018-11-19 10:24   ` [PATCH v5 20/47] x86emul: basic AVX512F testing Jan Beulich
2018-11-19 10:25   ` [PATCH v5 21/47] x86emul: support AVX512{F, BW, DQ} integer broadcast insns Jan Beulich
2018-11-19 10:25   ` [PATCH v5 22/47] x86emul: basic AVX512VL testing Jan Beulich
2018-11-19 10:26   ` [PATCH v5 23/47] x86emul: support AVX512{F, BW} zero- and sign-extending moves Jan Beulich
2018-11-19 10:26   ` [PATCH v5 24/47] x86emul: support AVX512{F, BW} down conversion moves Jan Beulich
2018-11-19 10:28   ` [PATCH v5 25/47] x86emul: support AVX512{F, BW} integer unpack insns Jan Beulich
2018-11-19 10:28   ` [PATCH v5 26/47] x86emul: support AVX512{F, BW, _VBMI} full permute insns Jan Beulich
2018-11-19 10:29   ` [PATCH v5 27/47] x86emul: support AVX512{F, BW} integer shuffle insns Jan Beulich
2018-11-19 10:30   ` [PATCH v5 28/47] x86emul: support AVX512{BW, DQ} mask move insns Jan Beulich
2018-11-19 10:30   ` [PATCH v5 29/47] x86emul: basic AVX512BW testing Jan Beulich
2018-11-19 10:31   ` [PATCH v5 30/47] x86emul: basic AVX512DQ testing Jan Beulich
2018-11-19 10:31   ` [PATCH v5 31/47] x86emul: support AVX512F move high/low insns Jan Beulich
2018-11-19 10:31   ` [PATCH v5 32/47] x86emul: support AVX512F move duplicate insns Jan Beulich
2018-11-19 10:32   ` [PATCH v5 33/47] x86emul: support AVX512{F, BW, VBMI} permute insns Jan Beulich
2018-11-19 10:33   ` [PATCH v5 34/47] x86emul: support AVX512BW pack insns Jan Beulich
2018-11-19 10:33   ` [PATCH v5 35/47] x86emul: support AVX512F floating-point conversion insns Jan Beulich
2018-11-19 10:34   ` [PATCH v5 36/47] x86emul: support AVX512F legacy-equivalent packed int/FP " Jan Beulich
2018-11-19 10:35   ` [PATCH v5 37/47] x86emul: support AVX512F legacy-equivalent scalar " Jan Beulich
2018-11-19 10:36   ` [PATCH v5 38/47] x86emul: support AVX512DQ packed quad-int/FP " Jan Beulich
2018-11-19 10:37   ` [PATCH v5 39/47] x86emul: support AVX512{F, DQ} uint-to-FP " Jan Beulich
2018-11-19 10:37   ` [PATCH v5 40/47] x86emul: support AVX512{F, DQ} FP-to-uint " Jan Beulich
2018-11-19 10:38   ` [PATCH v5 41/47] x86emul: support remaining AVX512F legacy-equivalent insns Jan Beulich
2018-11-19 10:38   ` [PATCH v5 42/47] x86emul: support remaining AVX512BW " Jan Beulich
2018-11-19 10:39   ` [PATCH v5 43/47] x86emul: support AVX512{F, ER} reciprocal insns Jan Beulich
2018-11-19 10:39   ` [PATCH v5 44/47] x86emul: support AVX512F floating point manipulation insns Jan Beulich
2018-11-19 10:40   ` [PATCH v5 45/47] x86emul: support AVX512DQ " Jan Beulich
2018-11-19 10:40   ` [PATCH v5 46/47] x86emul: support AVX512{F, _VBMI2} compress/expand insns Jan Beulich
2018-11-19 10:41   ` [PATCH v5 47/47] x86emul: support remaining misc AVX512{F, BW} insns Jan Beulich
2018-12-06  9:45 ` [PATCH v6 00/42] x86emul: fair parts of AVX512 support Jan Beulich
2018-12-06  9:51   ` [PATCH v6 01/42] x86emul: support AVX512{F, BW} shift/rotate insns Jan Beulich
2018-12-06  9:51   ` [PATCH v6 02/42] x86emul: support AVX512{F, BW, DQ} extract insns Jan Beulich
2018-12-06  9:51   ` [PATCH v6 03/42] x86emul: support AVX512{F, BW, DQ} insert insns Jan Beulich
2018-12-06  9:52   ` [PATCH v6 04/42] x86emul: basic AVX512F testing Jan Beulich
2018-12-06  9:53   ` [PATCH v6 05/42] x86emul: support AVX512{F, BW, DQ} integer broadcast insns Jan Beulich
2018-12-06  9:53   ` [PATCH v6 06/42] x86emul: basic AVX512VL testing Jan Beulich
2018-12-06  9:53   ` [PATCH v6 07/42] x86emul: support AVX512{F, BW} zero- and sign-extending moves Jan Beulich
2018-12-06  9:54   ` [PATCH v6 08/42] x86emul: support AVX512{F, BW} down conversion moves Jan Beulich
2018-12-06  9:54   ` [PATCH v6 09/42] x86emul: support AVX512{F, BW} integer unpack insns Jan Beulich
2018-12-06  9:55   ` [PATCH v6 10/42] x86emul: support AVX512{F, BW, _VBMI} full permute insns Jan Beulich
2018-12-06  9:55   ` [PATCH v6 11/42] x86emul: support AVX512{F, BW} integer shuffle insns Jan Beulich
2018-12-06  9:55   ` [PATCH v6 12/42] x86emul: support AVX512{BW, DQ} mask move insns Jan Beulich
2018-12-06  9:56   ` [PATCH v6 13/42] x86emul: basic AVX512BW testing Jan Beulich
2018-12-06  9:57   ` [PATCH v6 14/42] x86emul: basic AVX512DQ testing Jan Beulich
2018-12-06  9:57   ` [PATCH v6 15/42] x86emul: support AVX512F move high/low insns Jan Beulich
2018-12-06  9:58   ` [PATCH v6 16/42] x86emul: support AVX512F move duplicate insns Jan Beulich
2018-12-06  9:59   ` [PATCH v6 17/42] x86emul: support AVX512{F, BW, _VBMI} permute insns Jan Beulich
2018-12-06  9:59   ` [PATCH v6 18/42] x86emul: support AVX512BW pack insns Jan Beulich
2018-12-06 10:00   ` [PATCH v6 19/42] x86emul: support AVX512F floating-point conversion insns Jan Beulich
2018-12-06 10:00   ` [PATCH v6 20/42] x86emul: support AVX512F legacy-equivalent packed int/FP " Jan Beulich
2018-12-06 10:01   ` [PATCH v6 21/42] x86emul: support AVX512F legacy-equivalent scalar " Jan Beulich
2018-12-06 10:01   ` [PATCH v6 22/42] x86emul: support AVX512DQ packed quad-int/FP " Jan Beulich
2018-12-06 10:02   ` [PATCH v6 23/42] x86emul: support AVX512{F, DQ} uint-to-FP " Jan Beulich
2018-12-06 10:02   ` [PATCH v6 24/42] x86emul: support AVX512{F, DQ} FP-to-uint " Jan Beulich
2018-12-06 10:04   ` [PATCH v6 25/42] x86emul: support remaining AVX512F legacy-equivalent insns Jan Beulich
2018-12-06 10:04   ` [PATCH v6 26/42] x86emul: support remaining AVX512BW " Jan Beulich
2018-12-06 10:04   ` [PATCH v6 27/42] x86emul: support AVX512{F, ER} reciprocal insns Jan Beulich
2018-12-06 10:05   ` [PATCH v6 28/42] x86emul: support AVX512F floating point manipulation insns Jan Beulich
2018-12-06 10:05   ` [PATCH v6 29/42] x86emul: support AVX512DQ " Jan Beulich
2018-12-06 10:06   ` [PATCH v6 30/42] x86emul: support AVX512{F, _VBMI2} compress/expand insns Jan Beulich
2018-12-06 10:07   ` [PATCH v6 31/42] x86emul: support remaining misc AVX512{F, BW} insns Jan Beulich
2018-12-06 10:07   ` [PATCH v6 32/42] x86emul: support AVX512F gather insns Jan Beulich
2018-12-06 10:08   ` [PATCH v6 33/42] x86emul: add high register S/G test cases Jan Beulich
2018-12-06 10:08   ` [PATCH v6 34/42] x86emul: support AVX512F scatter insns Jan Beulich
2018-12-06 10:09   ` [PATCH v6 35/42] x86emul: support AVX512PF insns Jan Beulich
2018-12-06 10:09   ` [PATCH v6 36/42] x86emul: support AVX512CD insns Jan Beulich
2018-12-06 10:10   ` [PATCH v6 37/42] x86emul: complete support of AVX512_VBMI insns Jan Beulich
2018-12-06 10:10   ` [PATCH v6 38/42] x86emul: support of AVX512* population count insns Jan Beulich
2018-12-06 10:11   ` [PATCH v6 39/42] x86emul: support of AVX512_IFMA insns Jan Beulich
2018-12-06 10:11   ` [PATCH v6 40/42] x86emul: support remaining AVX512_VBMI2 insns Jan Beulich
2018-12-06 10:12   ` [PATCH v6 41/42] x86emul: support AVX512_4FMAPS insns Jan Beulich
2018-12-06 10:12   ` [PATCH v6 42/42] x86emul: support AVX512_4VNNIW insns Jan Beulich
2018-12-19 14:17 ` [PATCH v7 00/49] x86emul: remaining AVX512 support Jan Beulich
2018-12-19 14:34   ` Jan Beulich
2018-12-19 14:35   ` [PATCH v7 01/49] x86emul: rename evex.br to evex.brs Jan Beulich
2018-12-19 15:14     ` Andrew Cooper
2018-12-19 14:36   ` [PATCH v7 02/49] x86emul: support AVX512{F, BW} shift/rotate insns Jan Beulich
2018-12-19 16:00     ` Andrew Cooper
2018-12-19 14:36   ` [PATCH v7 03/49] x86emul: support AVX512{F, BW, DQ} extract insns Jan Beulich
2018-12-19 18:20     ` Andrew Cooper
2018-12-20  7:49       ` Jan Beulich
2018-12-19 14:37   ` [PATCH v7 04/49] x86emul: support AVX512{F, BW, DQ} insert insns Jan Beulich
2019-03-14 15:35     ` Andrew Cooper
2018-12-19 14:37   ` [PATCH v7 05/49] x86emul: basic AVX512F testing Jan Beulich
2019-03-14 15:42     ` Andrew Cooper
2018-12-19 14:38   ` [PATCH v7 06/49] x86emul: support AVX512{F, BW, DQ} integer broadcast insns Jan Beulich
2019-03-14 16:38     ` Andrew Cooper
2019-03-14 17:15       ` Jan Beulich
2019-03-15 16:39         ` Andrew Cooper
2019-03-18  9:45           ` Jan Beulich
2018-12-19 14:38   ` [PATCH v7 07/49] x86emul: basic AVX512VL testing Jan Beulich
2019-03-14 16:39     ` Andrew Cooper
2018-12-19 14:41   ` [PATCH v7 08/49] x86emul: support AVX512{F, BW} zero- and sign-extending moves Jan Beulich
2018-12-19 14:41   ` [PATCH v7 09/49] x86emul: support AVX512{F, BW} down conversion moves Jan Beulich
2018-12-19 14:42   ` [PATCH v7 10/49] x86emul: support AVX512{F, BW} integer unpack insns Jan Beulich
2018-12-19 14:42   ` [PATCH v7 11/49] x86emul: support AVX512{F, BW, _VBMI} full permute insns Jan Beulich
2018-12-19 14:43   ` [PATCH v7 12/49] x86emul: support AVX512{F, BW} integer shuffle insns Jan Beulich
2018-12-19 14:43   ` [PATCH v7 13/49] x86emul: support AVX512{BW, DQ} mask move insns Jan Beulich
2018-12-19 14:44   ` [PATCH v7 14/49] x86emul: basic AVX512BW testing Jan Beulich
2018-12-19 14:46   ` [PATCH v7 15/49] x86emul: basic AVX512DQ testing Jan Beulich
2018-12-19 14:46   ` [PATCH v7 16/49] x86emul: support AVX512F move high/low insns Jan Beulich
2018-12-19 14:47   ` [PATCH v7 17/49] x86emul: support AVX512F move duplicate insns Jan Beulich
2018-12-19 14:47   ` [PATCH v7 18/49] x86emul: support AVX512{F, BW, _VBMI} permute insns Jan Beulich
2018-12-19 14:48   ` [PATCH v7 19/49] x86emul: support AVX512BW pack insns Jan Beulich
2018-12-19 14:48   ` [PATCH v7 20/49] x86emul: support AVX512F floating-point conversion insns Jan Beulich
2018-12-19 14:48   ` [PATCH v7 21/49] x86emul: support AVX512F legacy-equivalent packed int/FP " Jan Beulich
2018-12-19 14:51   ` [PATCH v7 22/49] x86emul: support AVX512F legacy-equivalent scalar " Jan Beulich
2018-12-19 14:51   ` [PATCH v7 23/49] x86emul: support AVX512DQ packed quad-int/FP " Jan Beulich
2018-12-19 14:52   ` [PATCH v7 24/49] x86emul: support AVX512{F, DQ} uint-to-FP " Jan Beulich
2018-12-19 14:52   ` [PATCH v7 25/49] x86emul: support AVX512{F, DQ} FP-to-uint " Jan Beulich
2018-12-19 14:53   ` [PATCH v7 26/49] x86emul: support remaining AVX512F legacy-equivalent insns Jan Beulich
2018-12-19 14:53   ` [PATCH v7 27/49] x86emul: support remaining AVX512BW " Jan Beulich
2018-12-19 14:54   ` [PATCH v7 28/49] x86emul: support AVX512{F, ER} reciprocal insns Jan Beulich
2018-12-19 14:55   ` [PATCH v7 29/49] x86emul: support AVX512F floating point manipulation insns Jan Beulich
2018-12-19 14:55   ` [PATCH v7 30/49] x86emul: support AVX512DQ " Jan Beulich
2018-12-19 14:56   ` [PATCH v7 31/49] x86emul: support AVX512{F, _VBMI2} compress/expand insns Jan Beulich
2018-12-19 14:56   ` [PATCH v7 32/49] x86emul: support remaining misc AVX512{F, BW} insns Jan Beulich
2018-12-19 14:57   ` [PATCH v7 33/49] x86emul: support AVX512F gather insns Jan Beulich
2018-12-19 14:57   ` [PATCH v7 34/49] x86emul: add high register S/G test cases Jan Beulich
2018-12-19 14:58   ` [PATCH v7 35/49] x86emul: support AVX512F scatter insns Jan Beulich
2018-12-19 14:59   ` [PATCH v7 36/49] x86emul: support AVX512PF insns Jan Beulich
2018-12-19 14:59   ` [PATCH v7 37/49] x86emul: support AVX512CD insns Jan Beulich
2018-12-19 15:00   ` [PATCH v7 38/49] x86emul: complete support of AVX512_VBMI insns Jan Beulich
2018-12-19 15:00   ` [PATCH v7 39/49] x86emul: support of AVX512* population count insns Jan Beulich
2018-12-19 15:01   ` [PATCH v7 40/49] x86emul: support of AVX512_IFMA insns Jan Beulich
2018-12-19 15:01   ` [PATCH v7 42/49] x86emul: support remaining AVX512_VBMI2 insns Jan Beulich
2018-12-19 15:02   ` [PATCH v7 42/49] x86emul: support AVX512_4FMAPS insns Jan Beulich
2018-12-19 15:05   ` [PATCH v7 43/49] x86emul: support AVX512_4VNNIW insns Jan Beulich
2018-12-19 15:06   ` [PATCH v7 44/49] x86emul: support AVX512_VNNI insns Jan Beulich
2018-12-19 15:06   ` [PATCH v7 45/49] x86emul: support VPCLMULQDQ insns Jan Beulich
2018-12-19 15:07   ` [PATCH v7 46/49] x86emul: support VAES insns Jan Beulich
2018-12-19 15:07   ` [PATCH v7 47/49] x86emul: support GFNI insns Jan Beulich
2018-12-19 15:07   ` [PATCH v7 48/49] x86emul: restore ordering within main switch statement Jan Beulich
2018-12-19 15:08   ` [PATCH v7 49/49] tools: re-sync CPUID leaf 7 tables Jan Beulich
2019-03-14 11:07     ` Andrew Cooper
2019-03-15 10:30 ` [PATCH v8 00/50] x86emul: remaining AVX512 support Jan Beulich
2019-03-15 10:36   ` [PATCH v8 01/50] x86emul: no need to set fault_suppression to false for VMOVNT* Jan Beulich
2019-03-15 16:52     ` Andrew Cooper
2019-03-15 10:36   ` [PATCH v8 02/50] x86emul: support AVX512{F, BW, DQ} extract insns Jan Beulich
2019-03-15 17:51     ` Andrew Cooper
2019-03-15 10:37   ` [PATCH v8 03/50] x86emul: support AVX512{F, BW, DQ} insert insns Jan Beulich
2019-03-15 10:38   ` [PATCH v8 04/50] x86emul: basic AVX512F testing Jan Beulich
2019-03-15 10:39   ` [PATCH v8 05/50] x86emul: support AVX512{F, BW, DQ} integer broadcast insns Jan Beulich
2019-03-15 10:39   ` [PATCH v8 06/50] x86emul: basic AVX512VL testing Jan Beulich
2019-03-15 10:40   ` [PATCH v8 07/50] x86emul: support AVX512{F, BW} zero- and sign-extending moves Jan Beulich
2019-03-15 18:02     ` Andrew Cooper
2019-03-15 10:40   ` [PATCH v8 08/50] x86emul: support AVX512{F, BW} down conversion moves Jan Beulich
2019-03-15 18:10     ` Andrew Cooper
2019-03-15 10:41   ` [PATCH v8 09/50] x86emul: support AVX512{F, BW} integer unpack insns Jan Beulich
2019-03-15 18:21     ` Andrew Cooper
2019-03-18  9:55       ` Jan Beulich
2019-05-20 12:11         ` Andrew Cooper
2019-05-20 12:11           ` [Xen-devel] " Andrew Cooper
2019-03-15 10:41   ` [PATCH v8 10/50] x86emul: support AVX512{F, BW, _VBMI} full permute insns Jan Beulich
2019-05-17 16:50     ` Andrew Cooper
2019-05-17 16:50       ` [Xen-devel] " Andrew Cooper
2019-05-20  6:55       ` Jan Beulich
2019-05-20  6:55         ` [Xen-devel] " Jan Beulich
2019-05-20 12:10         ` Andrew Cooper
2019-05-20 12:10           ` [Xen-devel] " Andrew Cooper
2019-03-15 10:43   ` [PATCH v8 11/50] x86emul: support AVX512{F, BW} integer shuffle insns Jan Beulich
2019-05-17 17:01     ` Andrew Cooper
2019-05-17 17:01       ` [Xen-devel] " Andrew Cooper
2019-03-15 10:43   ` [PATCH v8 12/50] x86emul: support AVX512{BW, DQ} mask move insns Jan Beulich
2019-05-17 17:02     ` Andrew Cooper
2019-05-17 17:02       ` [Xen-devel] " Andrew Cooper
2019-03-15 10:43   ` [PATCH v8 13/50] x86emul: basic AVX512BW testing Jan Beulich
2019-05-17 17:03     ` Andrew Cooper
2019-05-17 17:03       ` [Xen-devel] " Andrew Cooper
2019-03-15 10:44   ` [PATCH v8 14/50] x86emul: basic AVX512DQ testing Jan Beulich
2019-05-17 17:03     ` Andrew Cooper
2019-05-17 17:03       ` [Xen-devel] " Andrew Cooper
2019-03-15 10:44   ` [PATCH v8 15/50] x86emul: support AVX512F move high/low insns Jan Beulich
2019-05-21 10:59     ` Andrew Cooper
2019-05-21 10:59       ` [Xen-devel] " Andrew Cooper
2019-03-15 10:45   ` [PATCH v8 16/50] x86emul: support AVX512F move duplicate insns Jan Beulich
2019-05-21 11:09     ` Andrew Cooper
2019-05-21 11:09       ` [Xen-devel] " Andrew Cooper
2019-03-15 10:46   ` [PATCH v8 17/50] x86emul: support AVX512{F, BW, _VBMI} permute insns Jan Beulich
2019-05-21 11:24     ` Andrew Cooper
2019-05-21 11:24       ` [Xen-devel] " Andrew Cooper
2019-03-15 10:46   ` [PATCH v8 18/50] x86emul: support AVX512BW pack insns Jan Beulich
2019-05-21 11:26     ` Andrew Cooper
2019-05-21 11:26       ` [Xen-devel] " Andrew Cooper
2019-03-15 10:47   ` [PATCH v8 19/50] x86emul: support AVX512F floating-point conversion insns Jan Beulich
2019-05-21 11:33     ` Andrew Cooper
2019-05-21 11:33       ` [Xen-devel] " Andrew Cooper
2019-05-21 15:46       ` Jan Beulich
2019-05-21 15:46         ` [Xen-devel] " Jan Beulich
2019-05-23 16:08         ` Andrew Cooper
2019-05-23 16:08           ` [Xen-devel] " Andrew Cooper
2019-03-15 10:47   ` [PATCH v8 20/50] x86emul: support AVX512F legacy-equivalent packed int/FP " Jan Beulich
2019-05-21 11:37     ` Andrew Cooper
2019-05-21 11:37       ` [Xen-devel] " Andrew Cooper
2019-03-15 10:52   ` [PATCH v8 21/50] x86emul: support AVX512F legacy-equivalent scalar " Jan Beulich
2019-05-21 11:44     ` Andrew Cooper
2019-05-21 11:44       ` [Xen-devel] " Andrew Cooper
2019-03-15 10:52   ` [PATCH v8 22/50] x86emul: support AVX512DQ packed quad-int/FP " Jan Beulich
2019-05-21 11:53     ` Andrew Cooper
2019-05-21 11:53       ` [Xen-devel] " Andrew Cooper
2019-03-15 10:53   ` [PATCH v8 23/50] x86emul: support AVX512{F, DQ} uint-to-FP " Jan Beulich
2019-05-21 11:58     ` Andrew Cooper
2019-05-21 11:58       ` [Xen-devel] " Andrew Cooper
2019-03-15 10:54   ` [PATCH v8 24/50] x86emul: support AVX512{F, DQ} FP-to-uint " Jan Beulich
2019-05-21 12:09     ` Andrew Cooper
2019-05-21 12:09       ` [Xen-devel] " Andrew Cooper
2019-03-15 10:54   ` [PATCH v8 25/50] x86emul: support remaining AVX512F legacy-equivalent insns Jan Beulich
2019-05-21 13:06     ` Andrew Cooper
2019-05-21 13:06       ` [Xen-devel] " Andrew Cooper
2019-03-15 10:54   ` [PATCH v8 26/50] x86emul: support remaining AVX512BW " Jan Beulich
2019-05-21 13:08     ` Andrew Cooper
2019-05-21 13:08       ` [Xen-devel] " Andrew Cooper
2019-05-21 13:34       ` Jan Beulich
2019-05-21 13:34         ` [Xen-devel] " Jan Beulich
2019-05-23 16:10     ` Andrew Cooper
2019-05-23 16:10       ` [Xen-devel] " Andrew Cooper
2019-03-15 10:55   ` [PATCH v8 27/50] x86emul: support AVX512{F, ER} reciprocal insns Jan Beulich
2019-05-23 16:15     ` Andrew Cooper
2019-05-23 16:15       ` [Xen-devel] " Andrew Cooper
2019-05-24  6:43       ` Jan Beulich
2019-05-24  6:43         ` [Xen-devel] " Jan Beulich
2019-05-24 20:48         ` Andrew Cooper
2019-05-24 20:48           ` [Xen-devel] " Andrew Cooper
2019-05-27  8:02           ` Jan Beulich
2019-05-27  8:02             ` [Xen-devel] " Jan Beulich
2019-05-29 10:00             ` Andrew Cooper
2019-05-29 10:00               ` [Xen-devel] " Andrew Cooper
2019-03-15 10:56   ` [PATCH v8 28/50] x86emul: support AVX512F floating point manipulation insns Jan Beulich
2019-05-29 12:51     ` Andrew Cooper
2019-05-29 12:51       ` [Xen-devel] " Andrew Cooper
2019-05-29 13:15       ` Jan Beulich
2019-05-29 13:15         ` [Xen-devel] " Jan Beulich
2019-06-10 14:01         ` Andrew Cooper
2019-06-10 14:03     ` Andrew Cooper
2019-03-15 10:56   ` [PATCH v8 29/50] x86emul: support AVX512DQ " Jan Beulich
2019-06-10 14:06     ` [Xen-devel] " Andrew Cooper
2019-03-15 10:56   ` [PATCH v8 30/50] x86emul: support AVX512{F, _VBMI2} compress/expand insns Jan Beulich
2019-06-10 14:51     ` [Xen-devel] " Andrew Cooper
2019-06-11 10:20       ` Jan Beulich
2019-06-18 16:24         ` Andrew Cooper
2019-06-19  6:38           ` Jan Beulich
2019-03-15 10:58   ` [PATCH v8 31/50] x86emul: support remaining misc AVX512{F, BW} insns Jan Beulich
2019-06-18 16:42     ` [Xen-devel] " Andrew Cooper
2019-06-19  6:44       ` Jan Beulich
2019-03-15 10:58   ` [PATCH v8 32/50] x86emul: support AVX512F gather insns Jan Beulich
2019-06-19 12:05     ` [Xen-devel] " Andrew Cooper
2019-06-19 12:43       ` Jan Beulich
2019-03-15 10:59   ` [PATCH v8 33/50] x86emul: add high register S/G test cases Jan Beulich
2019-06-19 12:07     ` [Xen-devel] " Andrew Cooper
2019-03-15 10:59   ` [PATCH v8 34/50] x86emul: support AVX512F scatter insns Jan Beulich
2019-03-15 11:00   ` [PATCH v8 35/50] x86emul: support AVX512PF insns Jan Beulich
2019-03-15 11:00   ` [PATCH v8 36/50] x86emul: support AVX512CD insns Jan Beulich
2019-06-19 12:13     ` [Xen-devel] " Andrew Cooper
2019-03-15 11:01   ` [PATCH v8 37/50] x86emul: complete support of AVX512_VBMI insns Jan Beulich
2019-06-19 12:16     ` [Xen-devel] " Andrew Cooper
2019-03-15 11:01   ` [PATCH v8 38/50] x86emul: support of AVX512* population count insns Jan Beulich
2019-06-19 12:22     ` [Xen-devel] " Andrew Cooper
2019-06-19 12:48       ` Jan Beulich
2019-03-15 11:02   ` [PATCH v8 39/50] x86emul: support of AVX512_IFMA insns Jan Beulich
2019-06-19 12:23     ` [Xen-devel] " Andrew Cooper
2019-03-15 11:02   ` [PATCH v8 40/50] x86emul: support remaining AVX512_VBMI2 insns Jan Beulich
2019-06-19 12:25     ` [Xen-devel] " Andrew Cooper
2019-03-15 11:04   ` [PATCH v8 41/50] x86emul: support AVX512_4FMAPS insns Jan Beulich
2019-06-19 14:58     ` [Xen-devel] " Andrew Cooper
2019-06-21  6:50       ` Jan Beulich
2019-03-15 11:04   ` [PATCH v8 42/50] x86emul: support AVX512_4VNNIW insns Jan Beulich
2019-06-19 14:58     ` [Xen-devel] " Andrew Cooper
2019-03-15 11:04   ` [PATCH v8 43/50] x86emul: support AVX512_VNNI insns Jan Beulich
2019-06-19 15:01     ` [Xen-devel] " Andrew Cooper
2019-06-21  6:55       ` Jan Beulich
2019-03-15 11:05   ` [PATCH v8 44/50] x86emul: support VPCLMULQDQ insns Jan Beulich
2019-06-21 12:52     ` [Xen-devel] " Andrew Cooper
2019-06-21 13:44       ` Jan Beulich
2019-03-15 11:06   ` [PATCH v8 45/50] x86emul: support VAES insns Jan Beulich
2019-06-21 12:57     ` [Xen-devel] " Andrew Cooper
2019-03-15 11:06   ` [PATCH v8 46/50] x86emul: support GFNI insns Jan Beulich
2019-06-21 13:19     ` [Xen-devel] " Andrew Cooper
2019-06-21 13:33       ` Andrew Cooper
2019-06-21 14:00       ` Jan Beulich
2019-06-21 14:20         ` Andrew Cooper
2019-06-21 15:02           ` Jan Beulich
2019-06-25  6:48           ` Jan Beulich
2019-03-15 11:07   ` [PATCH v8 47/50] x86emul: restore ordering within main switch statement Jan Beulich
2019-06-21 13:20     ` [Xen-devel] " Andrew Cooper
2019-03-15 11:07   ` [PATCH v8 48/50] x86emul: add an AES/VAES test case to the harness Jan Beulich
2019-06-21 13:36     ` [Xen-devel] " Andrew Cooper
2019-06-21 14:04       ` Jan Beulich
2019-06-21 14:20         ` Andrew Cooper
2019-03-15 11:08   ` [PATCH v8 49/50] x86emul: add a SHA " Jan Beulich
2019-06-21 13:51     ` [Xen-devel] " Andrew Cooper
2019-06-21 14:10       ` Jan Beulich
2019-06-21 14:23         ` Andrew Cooper
2019-03-15 11:08   ` [PATCH v8 50/50] x86emul: add a PCLMUL/VPCLMUL " Jan Beulich
2019-06-21 13:58     ` [Xen-devel] " Andrew Cooper

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Xen-Devel Archive on lore.kernel.org

Archives are clonable:
	git clone --mirror https://lore.kernel.org/xen-devel/0 xen-devel/git/0.git
	git clone --mirror https://lore.kernel.org/xen-devel/1 xen-devel/git/1.git

	# If you have public-inbox 1.1+ installed, you may
	# initialize and index your mirror using the following commands:
	public-inbox-init -V2 xen-devel xen-devel/ https://lore.kernel.org/xen-devel \
		xen-devel@lists.xenproject.org xen-devel@lists.xen.org xen-devel@archiver.kernel.org
	public-inbox-index xen-devel

Example config snippet for mirrors

Newsgroup available over NNTP:
	nntp://nntp.lore.kernel.org/org.xenproject.lists.xen-devel


AGPL code for this site: git clone https://public-inbox.org/ public-inbox