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From: "Jan Beulich" <JBeulich@suse.com>
To: xen-devel <xen-devel@lists.xenproject.org>
Cc: George Dunlap <George.Dunlap@eu.citrix.com>,
	Andrew Cooper <andrew.cooper3@citrix.com>,
	Wei Liu <wei.liu2@citrix.com>,
	Roger Pau Monne <roger.pau@citrix.com>
Subject: [PATCH v8 49/50] x86emul: add a SHA test case to the harness
Date: Fri, 15 Mar 2019 05:08:05 -0600
Message-ID: <5C8B8795020000780021F32C@prv1-mh.provo.novell.com> (raw)
In-Reply-To: <5C8B7EC0020000780021F10B@prv1-mh.provo.novell.com>

Also use this for AVX512VL VPRO{L,R}{,V}D as well as some further shifts
testing.

Signed-off-by: Jan Beulich <jbeulich@suse.com>
---
v8: New.

--- a/tools/tests/x86_emulator/Makefile
+++ b/tools/tests/x86_emulator/Makefile
@@ -20,8 +20,9 @@ SIMD := 3dnow sse sse2 sse4 avx avx2 xop
 FMA := fma4 fma
 SG := avx2-sg avx512f-sg avx512vl-sg
 AES := ssse3-aes avx-aes avx2-vaes avx512bw-vaes
+SHA := sse4-sha avx-sha avx512f-sha
 GF := sse2-gf avx2-gf avx512bw-gf
-TESTCASES := blowfish $(SIMD) $(FMA) $(SG) $(AES) $(GF)
+TESTCASES := blowfish $(SIMD) $(FMA) $(SG) $(AES) $(SHA) $(GF)
 
 OPMASK := avx512f avx512dq avx512bw
 
@@ -148,6 +149,10 @@ define simd-aes-defs
 $(1)-cflags := $(foreach vec,$($(patsubst %-aes,sse,$(1))-vecs) $($(patsubst %-vaes,%,$(1))-vecs), \
 	         "-D_$(vec) -maes $(addprefix -m,$(subst -,$(space),$(1))) $(call non-sse,$(1)) -Os -DVEC_SIZE=$(vec)")
 endef
+define simd-sha-defs
+$(1)-cflags := $(foreach vec,$(sse-vecs), \
+	         "-D_$(vec) $(addprefix -m,$(subst -,$(space),$(1))) -Os -DVEC_SIZE=$(vec)")
+endef
 define simd-gf-defs
 $(1)-cflags := $(foreach vec,$($(1:-gf=)-vecs), \
 	         "-D_$(vec) -mgfni -m$(1:-gf=) $(call non-sse,$(1)) -Os -DVEC_SIZE=$(vec)")
@@ -159,6 +164,7 @@ endef
 $(foreach flavor,$(SIMD) $(FMA),$(eval $(call simd-defs,$(flavor))))
 $(foreach flavor,$(SG),$(eval $(call simd-sg-defs,$(flavor))))
 $(foreach flavor,$(AES),$(eval $(call simd-aes-defs,$(flavor))))
+$(foreach flavor,$(SHA),$(eval $(call simd-sha-defs,$(flavor))))
 $(foreach flavor,$(GF),$(eval $(call simd-gf-defs,$(flavor))))
 $(foreach flavor,$(OPMASK),$(eval $(call opmask-defs,$(flavor))))
 
@@ -212,10 +218,13 @@ $(addsuffix .c,$(SG)):
 $(addsuffix .c,$(AES)):
 	ln -sf simd-aes.c $@
 
+$(addsuffix .c,$(SHA)):
+	ln -sf simd-sha.c $@
+
 $(addsuffix .c,$(GF)):
 	ln -sf simd-gf.c $@
 
-$(addsuffix .h,$(SIMD) $(FMA) $(SG) $(AES) $(GF)): simd.h
+$(addsuffix .h,$(SIMD) $(FMA) $(SG) $(AES) $(SHA) $(GF)): simd.h
 
 xop.h avx512f.h: simd-fma.c
 
--- /dev/null
+++ b/tools/tests/x86_emulator/simd-sha.c
@@ -0,0 +1,392 @@
+#define INT_SIZE 4
+
+#include "simd.h"
+ENTRY(sha_test);
+
+#define SHA(op, a...) __builtin_ia32_sha ## op(a)
+
+#ifdef __AVX512F__
+# define ALL_TRUE (~0ULL >> (64 - ELEM_COUNT))
+# define eq(x, y) (B(pcmpeqd, _mask, x, y, -1) == ALL_TRUE)
+# define blend(x, y, sel) B(movdqa32_, _mask, y, x, sel)
+# define rot_c(f, r, x, n) B(pro ## f ## d, _mask, x, n, undef(), ~0)
+# define rot_s(f, r, x, n) ({ /* gcc does not support embedded broadcast */ \
+    vec_t r_; \
+    asm ( "vpro" #f "vd %2%{1to%c3%}, %1, %0" \
+          : "=v" (r_) \
+          : "v" (x), "m" (n), "i" (ELEM_COUNT) ); \
+    r_; \
+})
+# define rot_v(d, x, n) B(pro ## d ## vd, _mask, x, n, undef(), ~0)
+# define shift_s(d, x, n) ({ \
+    vec_t r_; \
+    asm ( "vps" #d "lvd %2%{1to%c3%}, %1, %0" \
+          : "=v" (r_) \
+          : "v" (x), "m" (n), "i" (ELEM_COUNT) ); \
+    r_; \
+})
+# define vshift(d, x, n) ({ /* gcc does not allow memory operands */ \
+    vec_t r_; \
+    asm ( "vps" #d "ldq %2, %1, %0" \
+          : "=v" (r_) : "m" (x), "i" ((n) * ELEM_SIZE) ); \
+    r_; \
+})
+#else
+# define to_bool(cmp) (__builtin_ia32_pmovmskb128(cmp) == 0xffff)
+# define eq(x, y) to_bool((x) == (y))
+# define blend(x, y, sel) \
+    ((vec_t)__builtin_ia32_pblendw128((vhi_t)(x), (vhi_t)(y), \
+                                      ((sel) & 1 ? 0x03 : 0) | \
+                                      ((sel) & 2 ? 0x0c : 0) | \
+                                      ((sel) & 4 ? 0x30 : 0) | \
+                                      ((sel) & 8 ? 0xc0 : 0)))
+# define rot_c(f, r, x, n) (sh ## f ## _c(x, n) | sh ## r ## _c(x, 32 - (n)))
+# define rot_s(f, r, x, n) ({ /* gcc does not allow memory operands */ \
+    vec_t r_, t_, n_ = (vec_t){ 32 } - (n); \
+    asm ( "ps" #f "ld %2, %0; ps" #r "ld %3, %1; por %1, %0" \
+          : "=&x" (r_), "=&x" (t_) \
+          : "m" (n), "m" (n_), "0" (x), "1" (x) ); \
+    r_; \
+})
+static inline unsigned int rotl(unsigned int x, unsigned int n)
+{
+    return (x << (n & 0x1f)) | (x >> ((32 - n) & 0x1f));
+}
+static inline unsigned int rotr(unsigned int x, unsigned int n)
+{
+    return (x >> (n & 0x1f)) | (x << ((32 - n) & 0x1f));
+}
+# define rot_v(d, x, n) ({ \
+    vec_t t_; \
+    unsigned int i_; \
+    for ( i_ = 0; i_ < ELEM_COUNT; ++i_ ) \
+        t_[i_] = rot ## d((x)[i_], (n)[i_]); \
+    t_; \
+})
+# define shift_s(d, x, n) ({ \
+    vec_t r_; \
+    asm ( "ps" #d "ld %1, %0" : "=&x" (r_) : "m" (n), "0" (x) ); \
+    r_; \
+})
+# define vshift(d, x, n) \
+    (vec_t)(__builtin_ia32_ps ## d ## ldqi128((vdi_t)(x), (n) * ELEM_SIZE * 8))
+#endif
+
+#define alignr(x, y, n) ((vec_t)__builtin_ia32_palignr128((vdi_t)(x), (vdi_t)(y), (n) * 8))
+#define hadd(x, y) __builtin_ia32_phaddd128(x, y)
+#define rol_c(x, n) rot_c(l, r, x, n)
+#define rol_s(x, n) rot_s(l, r, x, n)
+#define rol_v(x, n...) rot_v(l, x, n)
+#define ror_c(x, n) rot_c(r, l, x, n)
+#define ror_s(x, n) rot_s(r, l, x, n)
+#define ror_v(x, n...) rot_v(r, x, n)
+#define shl_c(x, n) __builtin_ia32_pslldi128(x, n)
+#define shl_s(x, n) shift_s(l, x, n)
+#define shr_c(x, n) __builtin_ia32_psrldi128(x, n)
+#define shr_s(x, n) shift_s(r, x, n)
+#define shuf(x, s) __builtin_ia32_pshufd(x, s)
+#define swap(x) shuf(x, 0b00011011)
+#define vshl(x, n) vshift(l, x, n)
+#define vshr(x, n) vshift(r, x, n)
+
+static inline vec_t sha256_sigma0(vec_t w)
+{
+    vec_t res;
+
+    touch(w);
+    res = ror_c(w, 7);
+    touch(w);
+    res ^= rol_c(w, 14);
+    touch(w);
+    res ^= shr_c(w, 3);
+    touch(w);
+
+    return res;
+}
+
+static inline vec_t sha256_sigma1(vec_t w)
+{
+    vec_t _17 = { 17 }, _19 = { 19 }, _10 = { 10 };
+
+    return ror_s(w, _17) ^ ror_s(w, _19) ^ shr_s(w, _10);
+}
+
+static inline vec_t sha256_Sigma0(vec_t w)
+{
+    vec_t res, n1 = { 0, 0, 2, 2 }, n2 = { 0, 0, 13, 13 }, n3 = { 0, 0, 10, 10 };
+
+    touch(n1);
+    res = ror_v(w, n1);
+    touch(n2);
+    res ^= ror_v(w, n2);
+    touch(n3);
+
+    return res ^ rol_v(w, n3);
+}
+
+static inline vec_t sha256_Sigma1(vec_t w)
+{
+    return ror_c(w, 6) ^ ror_c(w, 11) ^ rol_c(w, 7);
+}
+
+int sha_test(void)
+{
+    unsigned int i;
+    vec_t src, one = { 1 };
+    vqi_t raw = {};
+
+    for ( i = 1; i < VEC_SIZE; ++i )
+        raw[i] = i;
+    src = (vec_t)raw;
+
+    for ( i = 0; i < 256; i += VEC_SIZE )
+    {
+        vec_t x, y, tmp, hash = -src;
+        vec_t a, b, c, d, e, g, h;
+        unsigned int k, r;
+
+        touch(src);
+        x = SHA(1msg1, hash, src);
+        touch(src);
+        y = hash ^ alignr(hash, src, 8);
+        touch(src);
+
+        if ( !eq(x, y) ) return __LINE__;
+
+        touch(src);
+        x = SHA(1msg2, hash, src);
+        touch(src);
+        tmp = hash ^ alignr(src, hash, 12);
+        touch(tmp);
+        y = rol_c(tmp, 1);
+        tmp = hash ^ alignr(src, y, 12);
+        touch(tmp);
+        y = rol_c(tmp, 1);
+
+        if ( !eq(x, y) ) return __LINE__;
+
+        touch(src);
+        x = SHA(1msg2, hash, src);
+        touch(src);
+        tmp = rol_s(hash ^ alignr(src, hash, 12), one);
+        y = rol_s(hash ^ alignr(src, tmp, 12), one);
+
+        if ( !eq(x, y) ) return __LINE__;
+
+        touch(src);
+        x = SHA(1nexte, hash, src);
+        touch(src);
+        touch(hash);
+        tmp = rol_c(hash, 30);
+        tmp[2] = tmp[1] = tmp[0] = 0;
+
+        if ( !eq(x, src + tmp) ) return __LINE__;
+
+        /*
+         * SHA1RNDS4
+         *
+         * SRC1 = { A0, B0, C0, D0 }
+         * SRC2 = W' = { W[0]E0, W[1], W[2], W[3] }
+         *
+         * (NB that the notation is not C-like, i.e. elements are listed
+         * high-to-low everywhere in this comment.)
+         *
+         * In order to pick a simple rounds function, an immediate value of
+         * 1 is used; 3 would also be a possibility.
+         *
+         * Applying
+         *
+         * A1 = ROL5(A0) + (B0 ^ C0 ^ D0) + W'[0] + K
+         * E1 = D0
+         * D1 = C0
+         * C1 = ROL30(B0)
+         * B1 = A0
+         *
+         * iteratively four times and resolving round variable values to
+         * A<n> and B0, C0, and D0 we get
+         *
+         * A4 = ROL5(A3) + (A2 ^ ROL30(A1) ^ ROL30(A0)) + W'[3] + ROL30(B0) + K
+         * A3 = ROL5(A2) + (A1 ^ ROL30(A0) ^ ROL30(B0)) + W'[2] +       C0  + K
+         * A2 = ROL5(A1) + (A0 ^ ROL30(B0) ^       C0 ) + W'[1] +       D0  + K
+         * A1 = ROL5(A0) + (B0 ^       C0  ^       D0 ) + W'[0]             + K
+         *
+         * (respective per-column variable names:
+         *  y         a      b          c           d      src           e    k
+         * )
+         *
+         * with
+         *
+         * B4 = A3
+         * C4 = ROL30(A2)
+         * D4 = ROL30(A1)
+         * E4 = ROL30(A0)
+         *
+         * and hence
+         *
+         * DST = { A4, A3, ROL30(A2), ROL30(A1) }
+         */
+
+        touch(src);
+        x = SHA(1rnds4, hash, src, 1);
+        touch(src);
+
+        a = vshr(hash, 3);
+        b = vshr(hash, 2);
+        touch(hash);
+        d = rol_c(hash, 30);
+        touch(hash);
+        d = blend(d, hash, 0b0011);
+        c = vshr(d, 1);
+        e = vshl(d, 1);
+        tmp = (vec_t){};
+        k = rol_c(SHA(1rnds4, tmp, tmp, 1), 2)[0];
+
+        for ( r = 0; r < 4; ++r )
+        {
+            y = rol_c(a, 5) + (b ^ c ^ d) + swap(src) + e + k;
+
+            switch ( r )
+            {
+            case 0:
+                c[3] = rol_c(y, 30)[0];
+                /* fall through */
+            case 1:
+                b[r + 2] = y[r];
+                /* fall through */
+            case 2:
+                a[r + 1] = y[r];
+                break;
+            }
+
+            switch ( r )
+            {
+            case 3:
+                if ( a[3] != y[2] ) return __LINE__;
+                /* fall through */
+            case 2:
+                if ( a[2] != y[1] ) return __LINE__;
+                if ( b[3] != y[1] ) return __LINE__;
+                /* fall through */
+            case 1:
+                if ( a[1] != y[0] ) return __LINE__;
+                if ( b[2] != y[0] ) return __LINE__;
+                if ( c[3] != rol_c(y, 30)[0] ) return __LINE__;
+                break;
+            }
+        }
+
+        a = blend(rol_c(y, 30), y, 0b1100);
+
+        if ( !eq(x, a) ) return __LINE__;
+
+        touch(src);
+        x = SHA(256msg1, hash, src);
+        touch(src);
+        y = hash + sha256_sigma0(alignr(src, hash, 4));
+
+        if ( !eq(x, y) ) return __LINE__;
+
+        touch(src);
+        x = SHA(256msg2, hash, src);
+        touch(src);
+        tmp = hash + sha256_sigma1(alignr(hash, src, 8));
+        y = hash + sha256_sigma1(alignr(tmp, src, 8));
+
+        if ( !eq(x, y) ) return __LINE__;
+
+        /*
+         * SHA256RNDS2
+         *
+         * SRC1 = { C0, D0, G0, H0 }
+         * SRC2 = { A0, B0, E0, F0 }
+         * XMM0 = W' = { ?, ?, WK1, WK0 }
+         *
+         * (NB that the notation again is not C-like, i.e. elements are listed
+         * high-to-low everywhere in this comment.)
+         *
+         * Ch(E,F,G) = (E & F) ^ (~E & G)
+         * Maj(A,B,C) = (A & B) ^ (A & C) ^ (B & C)
+         *
+         * Σ0(A) = ROR2(A) ^ ROR13(A) ^ ROR22(A)
+         * Σ1(E) = ROR6(E) ^ ROR11(E) ^ ROR25(E)
+         *
+         * Applying
+         *
+         * A1 = Ch(E0, F0, G0) + Σ1(E0) + WK0 + H0 + Maj(A0, B0, C0) + Σ0(A0)
+         * B1 = A0
+         * C1 = B0
+         * D1 = C0
+         * E1 = Ch(E0, F0, G0) + Σ1(E0) + WK0 + H0 + D0
+         * F1 = E0
+         * G1 = F0
+         * H1 = G0
+         *
+         * iteratively four times and resolving round variable values to
+         * A<n> / E<n> and B0, C0, D0, F0, G0, and H0 we get
+         *
+         * A2 = Ch(E1, E0, F0) + Σ1(E1) + WK1 + G0 + Maj(A1, A0, B0) + Σ0(A1)
+         * A1 = Ch(E0, F0, G0) + Σ1(E0) + WK0 + H0 + Maj(A0, B0, C0) + Σ0(A0)
+         * E2 = Ch(E1, E0, F0) + Σ1(E1) + WK1 + G0 + C0
+         * E1 = Ch(E0, F0, G0) + Σ1(E0) + WK0 + H0 + D0
+         *
+         * with
+         *
+         * B2 = A1
+         * F2 = E1
+         *
+         * and hence
+         *
+         * DST = { A2, A1, E2, E1 }
+         *
+         * which we can simplify a little, by letting A0, B0, and E0 be zero
+         * and F0 = ~G0, and by then utilizing
+         *
+         * Ch(0, 0, x) = x
+         * Ch(x, 0, y) = ~x & y
+         * Maj(x, 0, 0) = Maj(0, x, 0) = Maj(0, 0, x) = 0
+         *
+         * A2 = (~E1 & F0) + Σ1(E1) + WK1 + G0 + Σ0(A1)
+         * A1 = (~E0 & G0) + Σ1(E0) + WK0 + H0 + Σ0(A0)
+         * E2 = (~E1 & F0) + Σ1(E1) + WK1 + G0 + C0
+         * E1 = (~E0 & G0) + Σ1(E0) + WK0 + H0 + D0
+         *
+         * (respective per-column variable names:
+         *  y      e    g        e    src    h    d
+         * )
+         */
+
+        tmp = (vec_t){ ~hash[1] };
+        touch(tmp);
+        x = SHA(256rnds2, hash, tmp, src);
+        touch(tmp);
+
+        e = y = (vec_t){};
+        d = alignr(y, hash, 8);
+        g = (vec_t){ hash[1], tmp[0], hash[1], tmp[0] };
+        h = shuf(hash, 0b01000100);
+
+        for ( r = 0; r < 2; ++r )
+        {
+            y = (~e & g) + sha256_Sigma1(e) + shuf(src, 0b01000100) +
+                h + sha256_Sigma0(d);
+
+            if ( !r )
+            {
+                d[3] = y[2];
+                e[3] = e[1] = y[0];
+            }
+            else if ( d[3] != y[2] )
+                return __LINE__;
+            else if ( e[1] != y[0] )
+                return __LINE__;
+            else if ( e[3] != y[0] )
+                return __LINE__;
+        }
+
+        if ( !eq(x, y) ) return __LINE__;
+
+        src += 0x01010101 * VEC_SIZE;
+    }
+
+    return 0;
+}
--- a/tools/tests/x86_emulator/test_x86_emulator.c
+++ b/tools/tests/x86_emulator/test_x86_emulator.c
@@ -14,8 +14,10 @@ asm ( ".pushsection .test, \"ax\", @prog
 #include "sse2-gf.h"
 #include "ssse3-aes.h"
 #include "sse4.h"
+#include "sse4-sha.h"
 #include "avx.h"
 #include "avx-aes.h"
+#include "avx-sha.h"
 #include "fma4.h"
 #include "fma.h"
 #include "avx2.h"
@@ -28,6 +30,7 @@ asm ( ".pushsection .test, \"ax\", @prog
 #include "avx512bw-opmask.h"
 #include "avx512f.h"
 #include "avx512f-sg.h"
+#include "avx512f-sha.h"
 #include "avx512vl-sg.h"
 #include "avx512bw.h"
 #include "avx512bw-vaes.h"
@@ -155,6 +158,21 @@ static bool simd_check_avx512vbmi_vl(voi
     return cpu_has_avx512_vbmi && cpu_has_avx512vl;
 }
 
+static bool simd_check_sse4_sha(void)
+{
+    return cpu_has_sha && cpu_has_sse4_2;
+}
+
+static bool simd_check_avx_sha(void)
+{
+    return cpu_has_sha && cpu_has_avx;
+}
+
+static bool simd_check_avx512f_sha_vl(void)
+{
+    return cpu_has_sha && cpu_has_avx512vl;
+}
+
 static bool simd_check_avx2_vaes(void)
 {
     return cpu_has_aesni && cpu_has_vaes && cpu_has_avx2;
@@ -450,6 +468,9 @@ static const struct {
     AVX512VL(_VBMI+VL u16x8, avx512vbmi,    16u2),
     AVX512VL(_VBMI+VL s16x16, avx512vbmi,   32i2),
     AVX512VL(_VBMI+VL u16x16, avx512vbmi,   32u2),
+    SIMD(SHA,                sse4_sha,        16),
+    SIMD(AVX+SHA,             avx_sha,        16),
+    AVX512VL(VL+SHA,      avx512f_sha,        16),
     SIMD(VAES (VEX/x32),    avx2_vaes,        32),
     SIMD(VAES (EVEX/x64), avx512bw_vaes,      64),
     AVX512VL(VL+VAES (x16), avx512bw_vaes,    16),
--- a/tools/tests/x86_emulator/x86-emulate.h
+++ b/tools/tests/x86_emulator/x86-emulate.h
@@ -142,6 +142,7 @@ static inline bool xcr0_mask(uint64_t ma
 #define cpu_has_avx512_ifma (cp.feat.avx512_ifma && xcr0_mask(0xe6))
 #define cpu_has_avx512er  (cp.feat.avx512er && xcr0_mask(0xe6))
 #define cpu_has_avx512cd  (cp.feat.avx512cd && xcr0_mask(0xe6))
+#define cpu_has_sha        cp.feat.sha
 #define cpu_has_avx512bw  (cp.feat.avx512bw && xcr0_mask(0xe6))
 #define cpu_has_avx512vl  (cp.feat.avx512vl && xcr0_mask(0xe6))
 #define cpu_has_avx512_vbmi (cp.feat.avx512_vbmi && xcr0_mask(0xe6))




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Thread overview: 465+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-08-09  8:15 [PATCH 0/6] x86emul: fixes, improvements, and beginnings of AVX512 support Jan Beulich
2018-08-09  8:23 ` [PATCH 1/6] x86emul: fix FMA scalar operand sizes Jan Beulich
2018-08-09  8:24 ` [PATCH 2/6] x86emul: extend MASKMOV{Q,DQU} tests Jan Beulich
2018-08-09  8:24 ` [PATCH 3/6] x86emul: support AVX512 opmask insns Jan Beulich
2018-08-09  8:25 ` [PATCH 4/6] x86emul: clean up AVX2 insn use in test harness Jan Beulich
2018-08-09  8:25 ` [PATCH 5/6] x86emul: correct EVEX decoding Jan Beulich
2018-08-09  8:26 ` [PATCH 6/6] x86emul: generalize vector length handling for AVX512/EVEX Jan Beulich
2018-08-29 14:20 ` [PATCH v2 0/6] x86emul: fixes, improvements, and beginnings of AVX512 support Jan Beulich
2018-08-29 14:23   ` [PATCH v2 1/6] x86emul: fix FMA scalar operand sizes Jan Beulich
2018-09-03 16:43     ` Andrew Cooper
2018-09-04  7:52       ` Jan Beulich
2018-08-29 14:23   ` [PATCH v2 2/6] x86emul: extend MASKMOV{Q,DQU} tests Jan Beulich
2018-09-03 16:44     ` [PATCH v2 2/6] x86emul: extend MASKMOV{Q, DQU} tests Andrew Cooper
2018-08-29 14:24   ` [PATCH v2 3/6] x86emul: support AVX512 opmask insns Jan Beulich
2018-09-03 17:57     ` Andrew Cooper
2018-09-04  7:58       ` Jan Beulich
2018-08-29 14:24   ` [PATCH v2 4/6] x86emul: clean up AVX2 insn use in test harness Jan Beulich
2018-09-03 18:04     ` Andrew Cooper
2018-08-29 14:25   ` [PATCH v2 5/6] x86emul: correct EVEX decoding Jan Beulich
2018-09-04 10:48     ` Andrew Cooper
2018-09-04 12:48       ` Jan Beulich
2018-08-29 14:25   ` [PATCH v2 6/6] x86emul: generalize vector length handling for AVX512/EVEX Jan Beulich
2018-09-04 11:02     ` Andrew Cooper
2018-09-04 12:50       ` Jan Beulich
2018-09-18 11:46 ` [PATCH v3 00/34] x86emul: fixes, improvements, and beginnings of AVX512 support Jan Beulich
2018-09-18 11:53   ` [PATCH v3 01/34] x86emul: support AVX512 opmask insns Jan Beulich
2018-10-25 18:32     ` Andrew Cooper
2018-10-26  9:03       ` Jan Beulich
2018-10-26 11:29         ` Andrew Cooper
2018-10-26 11:59           ` Jan Beulich
2018-10-26 12:19             ` Andrew Cooper
2018-10-26 12:34               ` Jan Beulich
2018-09-18 11:53   ` [PATCH v3 02/34] x86/HVM: grow MMIO cache data size to 64 bytes Jan Beulich
2018-09-18 16:05     ` Paul Durrant
2018-10-25 18:36     ` Andrew Cooper
2018-10-26  9:04       ` Jan Beulich
2018-10-26 11:29         ` Andrew Cooper
2018-09-18 11:55   ` [PATCH v3 03/34] x86emul: correct EVEX decoding Jan Beulich
2018-09-18 11:55   ` [PATCH v3 04/34] x86emul: generalize vector length handling for AVX512/EVEX Jan Beulich
2018-09-18 11:56   ` [PATCH v3 05/34] x86emul: support basic AVX512 moves Jan Beulich
2018-09-18 11:57   ` [PATCH v3 06/34] x86emul: test for correct EVEX Disp8 scaling Jan Beulich
2018-09-18 11:57   ` [PATCH v3 07/34] x86emul: use AVX512 logic for emulating V{, P}MASKMOV* Jan Beulich
2018-09-18 11:58   ` [PATCH v3 08/34] x86emul: support AVX512F legacy-equivalent arithmetic FP insns Jan Beulich
2018-09-18 11:59   ` [PATCH v3 09/34] x86emul: support AVX512DQ logic " Jan Beulich
2018-09-18 11:59   ` [PATCH v3 10/34] x86emul: support AVX512F "normal" FP compare insns Jan Beulich
2018-09-18 12:00   ` [PATCH v3 11/34] x86emul: support AVX512F misc legacy-equivalent FP insns Jan Beulich
2018-09-18 12:00   ` [PATCH v3 12/34] x86emul: support AVX512F fused-multiply-add insns Jan Beulich
2018-09-18 12:01   ` [PATCH v3 13/34] x86emul: support AVX512F legacy-equivalent logic insns Jan Beulich
2018-09-18 12:02   ` [PATCH v3 14/34] x86emul: support AVX512{F, DQ} FP broadcast insns Jan Beulich
2018-09-18 12:03   ` [PATCH v3 15/34] x86emul: support AVX512F v{, u}comis{d, s} insns Jan Beulich
2018-09-18 12:03   ` [PATCH v3 16/34] x86emul/test: introduce eq() Jan Beulich
2018-09-18 12:04   ` [PATCH v3 17/34] x86emul: support AVX512{F, BW} packed integer compare insns Jan Beulich
2018-09-18 12:05   ` [PATCH v3 18/34] x86emul: support AVX512{F, BW} packed integer arithmetic insns Jan Beulich
2018-09-18 12:05   ` [PATCH v3 19/34] x86emul: use simd_128 also for legacy vector shift insns Jan Beulich
2018-09-18 12:05   ` [PATCH v3 20/34] x86emul: support AVX512{F, BW} shift/rotate insns Jan Beulich
2018-09-18 12:06   ` [PATCH v3 21/34] x86emul: support AVX512{F, BW, DQ} extract insns Jan Beulich
2018-09-18 12:07   ` [PATCH v3 22/34] x86emul: support AVX512{F, BW, DQ} insert insns Jan Beulich
2018-09-18 12:07   ` [PATCH v3 23/34] x86emul: basic AVX512F testing Jan Beulich
2018-09-18 12:08   ` [PATCH v3 24/34] x86emul: support AVX512{F, BW, DQ} integer broadcast insns Jan Beulich
2018-09-18 12:09   ` [PATCH v3 25/34] x86emul: basic AVX512VL testing Jan Beulich
2018-09-18 12:09   ` [PATCH v3 26/34] x86emul: support AVX512{F, BW} zero- and sign-extending moves Jan Beulich
2018-09-18 12:09   ` [PATCH v3 27/34] x86emul: support AVX512{F, BW} down conversion moves Jan Beulich
2018-09-18 12:10   ` [PATCH v3 28/34] x86emul: support AVX512{F, BW} integer unpack insns Jan Beulich
2018-09-18 12:11   ` [PATCH v3 29/34] x86emul: support AVX512{F, BW, _VBMI} full permute insns Jan Beulich
2018-09-18 12:11   ` [PATCH v3 29/34] x86emul: support AVX512{F, BW} integer shuffle insns Jan Beulich
2018-09-18 12:12   ` [PATCH v3 30/34] x86emul: support AVX512{BW, DQ} mask move insns Jan Beulich
2018-09-18 12:14   ` [PATCH v3 32/34] x86emul: basic AVX512BW testing Jan Beulich
2018-09-18 12:14   ` [PATCH v3 33/34] x86emul: basic AVX512DQ testing Jan Beulich
2018-09-18 12:14   ` [PATCH v3 34/34] x86emul: also allow running the 32-bit harness on a 64-bit distro Jan Beulich
2018-09-25 13:14 ` [PATCH v4 00/44] x86emul: fixes, improvements, and beginnings of AVX512 support Jan Beulich
2018-09-25 13:25   ` [PATCH v4 01/44] x86emul: support AVX512 opmask insns Jan Beulich
2018-09-26  6:06     ` Jan Beulich
2018-09-25 13:26   ` [PATCH v4 02/44] x86/HVM: grow MMIO cache data size to 64 bytes Jan Beulich
2018-09-25 13:27   ` [PATCH v4 03/44] x86emul: correct EVEX decoding Jan Beulich
2018-10-26 14:33     ` Andrew Cooper
2018-09-25 13:28   ` [PATCH v4 04/44] x86emul: generalize vector length handling for AVX512/EVEX Jan Beulich
2018-10-26 16:10     ` Andrew Cooper
2018-09-25 13:28   ` [PATCH v4 05/44] x86emul: support basic AVX512 moves Jan Beulich
2018-11-13 17:12     ` Andrew Cooper
2018-11-14 14:35       ` Jan Beulich
2018-11-14 16:26         ` Andrew Cooper
2018-11-15  9:54           ` Jan Beulich
2018-09-25 13:29   ` [PATCH v4 06/44] x86emul: test for correct EVEX Disp8 scaling Jan Beulich
2018-11-12 17:42     ` Andrew Cooper
2018-11-13 11:12       ` Jan Beulich
2018-11-13 15:45         ` Andrew Cooper
2018-11-14 14:17           ` Jan Beulich
2018-11-14 14:42             ` Andrew Cooper
2018-11-14 14:58               ` Jan Beulich
2018-09-25 13:29   ` [PATCH v4 07/44] x86emul: also allow running the 32-bit harness on a 64-bit distro Jan Beulich
2018-11-12 17:50     ` Andrew Cooper
2018-11-13 11:42       ` Jan Beulich
2018-11-13 15:58         ` Andrew Cooper
2018-11-14  8:42           ` Jan Beulich
2018-09-25 13:30   ` [PATCH v4 08/44] x86emul: use AVX512 logic for emulating V{, P}MASKMOV* Jan Beulich
2018-11-13 18:12     ` Andrew Cooper
2018-09-25 13:31   ` [PATCH v4 09/44] x86emul: support AVX512F legacy-equivalent arithmetic FP insns Jan Beulich
2018-11-13 18:21     ` Andrew Cooper
2018-09-25 13:32   ` [PATCH v4 10/44] x86emul: support AVX512DQ logic " Jan Beulich
2018-11-13 18:56     ` Andrew Cooper
2018-09-25 13:32   ` [PATCH v4 11/44] x86emul: support AVX512F "normal" FP compare insns Jan Beulich
2018-11-13 19:04     ` Andrew Cooper
2018-11-14 14:41       ` Jan Beulich
2018-11-14 14:45         ` Andrew Cooper
2018-09-25 13:33   ` [PATCH v4 12/44] x86emul: support AVX512F misc legacy-equivalent FP insns Jan Beulich
2018-11-13 19:17     ` Andrew Cooper
2018-09-25 13:33   ` [PATCH v4 13/44] x86emul: support AVX512F fused-multiply-add insns Jan Beulich
2018-11-13 19:28     ` Andrew Cooper
2018-09-25 13:34   ` [PATCH v4 14/44] x86emul: support AVX512F legacy-equivalent logic insns Jan Beulich
2018-11-13 19:30     ` Andrew Cooper
2018-09-25 13:35   ` [PATCH v4 15/44] x86emul: support AVX512{F, DQ} FP broadcast insns Jan Beulich
2018-11-13 19:37     ` Andrew Cooper
2018-09-25 13:35   ` [PATCH v4 16/44] x86emul: support AVX512F v{, u}comis{d, s} insns Jan Beulich
2018-11-13 19:39     ` Andrew Cooper
2018-09-25 13:36   ` [PATCH v4 17/44] x86emul/test: introduce eq() Jan Beulich
2018-10-26 11:31     ` Andrew Cooper
2018-09-25 13:37   ` [PATCH v4 18/44] x86emul: support AVX512{F, BW} packed integer compare insns Jan Beulich
2018-09-25 13:37   ` [PATCH v4 19/44] x86emul: support AVX512{F, BW} packed integer arithmetic insns Jan Beulich
2018-09-25 13:38   ` [PATCH v4 20/44] x86emul: use simd_128 also for legacy vector shift insns Jan Beulich
2018-09-25 13:39   ` [PATCH v4 21/44] x86emul: support AVX512{F, BW} shift/rotate insns Jan Beulich
2018-09-25 13:40   ` [PATCH v4 22/44] x86emul: support AVX512{F, BW, DQ} extract insns Jan Beulich
2018-09-25 13:40   ` [PATCH v4 23/44] x86emul: support AVX512{F, BW, DQ} insert insns Jan Beulich
2018-09-25 13:41   ` [PATCH v4 24/44] x86emul: basic AVX512F testing Jan Beulich
2018-09-25 13:41   ` [PATCH v4 25/44] x86emul: support AVX512{F, BW, DQ} integer broadcast insns Jan Beulich
2018-09-25 13:42   ` [PATCH v4 26/44] x86emul: basic AVX512VL testing Jan Beulich
2018-09-25 13:43   ` [PATCH v4 27/44] x86emul: support AVX512{F, BW} zero- and sign-extending moves Jan Beulich
2018-09-25 13:43   ` [PATCH v4 28/44] x86emul: support AVX512{F, BW} down conversion moves Jan Beulich
2018-09-25 13:44   ` [PATCH v4 29/44] x86emul: support AVX512{F, BW} integer unpack insns Jan Beulich
2018-09-25 13:44   ` [PATCH v4 30/44] x86emul: support AVX512{F, BW, _VBMI} full permute insns Jan Beulich
2018-09-25 13:46   ` [PATCH v4 31/44] x86emul: support AVX512{F, BW} integer shuffle insns Jan Beulich
2018-09-25 13:46   ` [PATCH v4 32/44] x86emul: support AVX512{BW, DQ} mask move insns Jan Beulich
2018-09-25 13:47   ` [PATCH v4 33/44] x86emul: basic AVX512BW testing Jan Beulich
2018-09-25 13:48   ` [PATCH v4 34/44] x86emul: basic AVX512DQ testing Jan Beulich
2018-09-25 13:48   ` [PATCH v4 35/44] x86emul: support AVX512F move high/low insns Jan Beulich
2018-09-25 13:49   ` [PATCH v4 36/44] x86emul: support AVX512F move duplicate insns Jan Beulich
2018-09-25 13:49   ` [PATCH v4 37/44] x86emul: support AVX512{F, BW, VBMI} permute insns Jan Beulich
2018-09-25 13:50   ` [PATCH v4 38/44] x86emul: support AVX512BW pack insns Jan Beulich
2018-09-25 13:51   ` [PATCH v4 39/44] x86emul: support AVX512F floating-point conversion insns Jan Beulich
2018-09-25 13:52   ` [PATCH v4 40/44] x86emul: support AVX512F legacy-equivalent packed int/FP " Jan Beulich
2018-09-25 13:53   ` [PATCH v4 41/44] x86emul: support AVX512F legacy-equivalent scalar " Jan Beulich
2018-09-25 13:53   ` [PATCH v4 42/44] x86emul: support AVX512DQ packed quad-int/FP " Jan Beulich
2018-09-25 13:54   ` [PATCH v4 43/44] x86emul: support AVX512{F, DQ} uint-to-FP " Jan Beulich
2018-09-25 13:55   ` [PATCH v4 44/44] x86emul: support AVX512{F, DQ} FP-to-uint " Jan Beulich
2018-11-19 10:00 ` [PATCH v5 00/47] x86emul: fair parts of AVX512 support Jan Beulich
2018-11-19 10:13   ` [PATCH v5 01/47] x86emul: introduce IMPOSSIBLE() Jan Beulich
2018-11-19 18:11     ` Andrew Cooper
2018-11-20  8:12       ` Jan Beulich
2018-11-19 10:13   ` [PATCH v5 02/47] x86emul: support basic AVX512 moves Jan Beulich
2018-11-19 18:35     ` Andrew Cooper
2018-11-19 10:14   ` [PATCH v5 03/47] x86emul: test for correct EVEX Disp8 scaling Jan Beulich
2018-11-19 18:35     ` Andrew Cooper
2018-11-19 10:14   ` [PATCH v5 04/47] x86emul: also allow running the 32-bit harness on a 64-bit distro Jan Beulich
2018-11-19 18:40     ` Andrew Cooper
2018-11-19 10:15   ` [PATCH v5 05/47] x86emul: use AVX512 logic for emulating V{, P}MASKMOV* Jan Beulich
2018-11-19 10:16   ` [PATCH v5 06/47] x86emul: support AVX512F legacy-equivalent arithmetic FP insns Jan Beulich
2018-11-19 10:16   ` [PATCH v5 07/47] x86emul: support AVX512DQ logic " Jan Beulich
2018-11-19 10:17   ` [PATCH v5 08/47] x86emul: support basic AVX512F FP compare insns Jan Beulich
2018-11-19 10:17   ` [PATCH v5 09/47] x86emul: support AVX512F misc legacy-equivalent FP insns Jan Beulich
2018-11-19 10:18   ` [PATCH v5 10/47] x86emul: support AVX512F fused-multiply-add insns Jan Beulich
2018-11-19 10:18   ` [PATCH v5 11/47] x86emul: support AVX512F legacy-equivalent logic insns Jan Beulich
2018-11-19 10:19   ` [PATCH v5 12/47] x86emul: support AVX512{F, DQ} FP broadcast insns Jan Beulich
2018-11-19 18:44     ` Andrew Cooper
2018-11-19 10:20   ` [PATCH v5 13/47] x86emul: support AVX512F v{, u}comis{d, s} insns Jan Beulich
2018-11-19 10:21   ` [PATCH v5 14/47] x86emul: support AVX512{F, BW} packed integer compare insns Jan Beulich
2018-11-19 19:09     ` Andrew Cooper
2018-11-19 10:21   ` [PATCH v5 15/47] x86emul: support AVX512{F, BW} packed integer arithmetic insns Jan Beulich
2018-11-19 19:18     ` Andrew Cooper
2018-11-19 10:22   ` [PATCH v5 16/47] x86emul: use simd_128 also for legacy vector shift insns Jan Beulich
2018-11-19 19:21     ` Andrew Cooper
2018-11-19 10:22   ` [PATCH v5 17/47] x86emul: support AVX512{F, BW} shift/rotate insns Jan Beulich
2018-11-19 10:23   ` [PATCH v5 18/47] x86emul: support AVX512{F, BW, DQ} extract insns Jan Beulich
2018-11-19 10:23   ` [PATCH v5 19/47] x86emul: support AVX512{F, BW, DQ} insert insns Jan Beulich
2018-11-19 10:24   ` [PATCH v5 20/47] x86emul: basic AVX512F testing Jan Beulich
2018-11-19 10:25   ` [PATCH v5 21/47] x86emul: support AVX512{F, BW, DQ} integer broadcast insns Jan Beulich
2018-11-19 10:25   ` [PATCH v5 22/47] x86emul: basic AVX512VL testing Jan Beulich
2018-11-19 10:26   ` [PATCH v5 23/47] x86emul: support AVX512{F, BW} zero- and sign-extending moves Jan Beulich
2018-11-19 10:26   ` [PATCH v5 24/47] x86emul: support AVX512{F, BW} down conversion moves Jan Beulich
2018-11-19 10:28   ` [PATCH v5 25/47] x86emul: support AVX512{F, BW} integer unpack insns Jan Beulich
2018-11-19 10:28   ` [PATCH v5 26/47] x86emul: support AVX512{F, BW, _VBMI} full permute insns Jan Beulich
2018-11-19 10:29   ` [PATCH v5 27/47] x86emul: support AVX512{F, BW} integer shuffle insns Jan Beulich
2018-11-19 10:30   ` [PATCH v5 28/47] x86emul: support AVX512{BW, DQ} mask move insns Jan Beulich
2018-11-19 10:30   ` [PATCH v5 29/47] x86emul: basic AVX512BW testing Jan Beulich
2018-11-19 10:31   ` [PATCH v5 30/47] x86emul: basic AVX512DQ testing Jan Beulich
2018-11-19 10:31   ` [PATCH v5 31/47] x86emul: support AVX512F move high/low insns Jan Beulich
2018-11-19 10:31   ` [PATCH v5 32/47] x86emul: support AVX512F move duplicate insns Jan Beulich
2018-11-19 10:32   ` [PATCH v5 33/47] x86emul: support AVX512{F, BW, VBMI} permute insns Jan Beulich
2018-11-19 10:33   ` [PATCH v5 34/47] x86emul: support AVX512BW pack insns Jan Beulich
2018-11-19 10:33   ` [PATCH v5 35/47] x86emul: support AVX512F floating-point conversion insns Jan Beulich
2018-11-19 10:34   ` [PATCH v5 36/47] x86emul: support AVX512F legacy-equivalent packed int/FP " Jan Beulich
2018-11-19 10:35   ` [PATCH v5 37/47] x86emul: support AVX512F legacy-equivalent scalar " Jan Beulich
2018-11-19 10:36   ` [PATCH v5 38/47] x86emul: support AVX512DQ packed quad-int/FP " Jan Beulich
2018-11-19 10:37   ` [PATCH v5 39/47] x86emul: support AVX512{F, DQ} uint-to-FP " Jan Beulich
2018-11-19 10:37   ` [PATCH v5 40/47] x86emul: support AVX512{F, DQ} FP-to-uint " Jan Beulich
2018-11-19 10:38   ` [PATCH v5 41/47] x86emul: support remaining AVX512F legacy-equivalent insns Jan Beulich
2018-11-19 10:38   ` [PATCH v5 42/47] x86emul: support remaining AVX512BW " Jan Beulich
2018-11-19 10:39   ` [PATCH v5 43/47] x86emul: support AVX512{F, ER} reciprocal insns Jan Beulich
2018-11-19 10:39   ` [PATCH v5 44/47] x86emul: support AVX512F floating point manipulation insns Jan Beulich
2018-11-19 10:40   ` [PATCH v5 45/47] x86emul: support AVX512DQ " Jan Beulich
2018-11-19 10:40   ` [PATCH v5 46/47] x86emul: support AVX512{F, _VBMI2} compress/expand insns Jan Beulich
2018-11-19 10:41   ` [PATCH v5 47/47] x86emul: support remaining misc AVX512{F, BW} insns Jan Beulich
2018-12-06  9:45 ` [PATCH v6 00/42] x86emul: fair parts of AVX512 support Jan Beulich
2018-12-06  9:51   ` [PATCH v6 01/42] x86emul: support AVX512{F, BW} shift/rotate insns Jan Beulich
2018-12-06  9:51   ` [PATCH v6 02/42] x86emul: support AVX512{F, BW, DQ} extract insns Jan Beulich
2018-12-06  9:51   ` [PATCH v6 03/42] x86emul: support AVX512{F, BW, DQ} insert insns Jan Beulich
2018-12-06  9:52   ` [PATCH v6 04/42] x86emul: basic AVX512F testing Jan Beulich
2018-12-06  9:53   ` [PATCH v6 05/42] x86emul: support AVX512{F, BW, DQ} integer broadcast insns Jan Beulich
2018-12-06  9:53   ` [PATCH v6 06/42] x86emul: basic AVX512VL testing Jan Beulich
2018-12-06  9:53   ` [PATCH v6 07/42] x86emul: support AVX512{F, BW} zero- and sign-extending moves Jan Beulich
2018-12-06  9:54   ` [PATCH v6 08/42] x86emul: support AVX512{F, BW} down conversion moves Jan Beulich
2018-12-06  9:54   ` [PATCH v6 09/42] x86emul: support AVX512{F, BW} integer unpack insns Jan Beulich
2018-12-06  9:55   ` [PATCH v6 10/42] x86emul: support AVX512{F, BW, _VBMI} full permute insns Jan Beulich
2018-12-06  9:55   ` [PATCH v6 11/42] x86emul: support AVX512{F, BW} integer shuffle insns Jan Beulich
2018-12-06  9:55   ` [PATCH v6 12/42] x86emul: support AVX512{BW, DQ} mask move insns Jan Beulich
2018-12-06  9:56   ` [PATCH v6 13/42] x86emul: basic AVX512BW testing Jan Beulich
2018-12-06  9:57   ` [PATCH v6 14/42] x86emul: basic AVX512DQ testing Jan Beulich
2018-12-06  9:57   ` [PATCH v6 15/42] x86emul: support AVX512F move high/low insns Jan Beulich
2018-12-06  9:58   ` [PATCH v6 16/42] x86emul: support AVX512F move duplicate insns Jan Beulich
2018-12-06  9:59   ` [PATCH v6 17/42] x86emul: support AVX512{F, BW, _VBMI} permute insns Jan Beulich
2018-12-06  9:59   ` [PATCH v6 18/42] x86emul: support AVX512BW pack insns Jan Beulich
2018-12-06 10:00   ` [PATCH v6 19/42] x86emul: support AVX512F floating-point conversion insns Jan Beulich
2018-12-06 10:00   ` [PATCH v6 20/42] x86emul: support AVX512F legacy-equivalent packed int/FP " Jan Beulich
2018-12-06 10:01   ` [PATCH v6 21/42] x86emul: support AVX512F legacy-equivalent scalar " Jan Beulich
2018-12-06 10:01   ` [PATCH v6 22/42] x86emul: support AVX512DQ packed quad-int/FP " Jan Beulich
2018-12-06 10:02   ` [PATCH v6 23/42] x86emul: support AVX512{F, DQ} uint-to-FP " Jan Beulich
2018-12-06 10:02   ` [PATCH v6 24/42] x86emul: support AVX512{F, DQ} FP-to-uint " Jan Beulich
2018-12-06 10:04   ` [PATCH v6 25/42] x86emul: support remaining AVX512F legacy-equivalent insns Jan Beulich
2018-12-06 10:04   ` [PATCH v6 26/42] x86emul: support remaining AVX512BW " Jan Beulich
2018-12-06 10:04   ` [PATCH v6 27/42] x86emul: support AVX512{F, ER} reciprocal insns Jan Beulich
2018-12-06 10:05   ` [PATCH v6 28/42] x86emul: support AVX512F floating point manipulation insns Jan Beulich
2018-12-06 10:05   ` [PATCH v6 29/42] x86emul: support AVX512DQ " Jan Beulich
2018-12-06 10:06   ` [PATCH v6 30/42] x86emul: support AVX512{F, _VBMI2} compress/expand insns Jan Beulich
2018-12-06 10:07   ` [PATCH v6 31/42] x86emul: support remaining misc AVX512{F, BW} insns Jan Beulich
2018-12-06 10:07   ` [PATCH v6 32/42] x86emul: support AVX512F gather insns Jan Beulich
2018-12-06 10:08   ` [PATCH v6 33/42] x86emul: add high register S/G test cases Jan Beulich
2018-12-06 10:08   ` [PATCH v6 34/42] x86emul: support AVX512F scatter insns Jan Beulich
2018-12-06 10:09   ` [PATCH v6 35/42] x86emul: support AVX512PF insns Jan Beulich
2018-12-06 10:09   ` [PATCH v6 36/42] x86emul: support AVX512CD insns Jan Beulich
2018-12-06 10:10   ` [PATCH v6 37/42] x86emul: complete support of AVX512_VBMI insns Jan Beulich
2018-12-06 10:10   ` [PATCH v6 38/42] x86emul: support of AVX512* population count insns Jan Beulich
2018-12-06 10:11   ` [PATCH v6 39/42] x86emul: support of AVX512_IFMA insns Jan Beulich
2018-12-06 10:11   ` [PATCH v6 40/42] x86emul: support remaining AVX512_VBMI2 insns Jan Beulich
2018-12-06 10:12   ` [PATCH v6 41/42] x86emul: support AVX512_4FMAPS insns Jan Beulich
2018-12-06 10:12   ` [PATCH v6 42/42] x86emul: support AVX512_4VNNIW insns Jan Beulich
2018-12-19 14:17 ` [PATCH v7 00/49] x86emul: remaining AVX512 support Jan Beulich
2018-12-19 14:34   ` Jan Beulich
2018-12-19 14:35   ` [PATCH v7 01/49] x86emul: rename evex.br to evex.brs Jan Beulich
2018-12-19 15:14     ` Andrew Cooper
2018-12-19 14:36   ` [PATCH v7 02/49] x86emul: support AVX512{F, BW} shift/rotate insns Jan Beulich
2018-12-19 16:00     ` Andrew Cooper
2018-12-19 14:36   ` [PATCH v7 03/49] x86emul: support AVX512{F, BW, DQ} extract insns Jan Beulich
2018-12-19 18:20     ` Andrew Cooper
2018-12-20  7:49       ` Jan Beulich
2018-12-19 14:37   ` [PATCH v7 04/49] x86emul: support AVX512{F, BW, DQ} insert insns Jan Beulich
2019-03-14 15:35     ` Andrew Cooper
2018-12-19 14:37   ` [PATCH v7 05/49] x86emul: basic AVX512F testing Jan Beulich
2019-03-14 15:42     ` Andrew Cooper
2018-12-19 14:38   ` [PATCH v7 06/49] x86emul: support AVX512{F, BW, DQ} integer broadcast insns Jan Beulich
2019-03-14 16:38     ` Andrew Cooper
2019-03-14 17:15       ` Jan Beulich
2019-03-15 16:39         ` Andrew Cooper
2019-03-18  9:45           ` Jan Beulich
2018-12-19 14:38   ` [PATCH v7 07/49] x86emul: basic AVX512VL testing Jan Beulich
2019-03-14 16:39     ` Andrew Cooper
2018-12-19 14:41   ` [PATCH v7 08/49] x86emul: support AVX512{F, BW} zero- and sign-extending moves Jan Beulich
2018-12-19 14:41   ` [PATCH v7 09/49] x86emul: support AVX512{F, BW} down conversion moves Jan Beulich
2018-12-19 14:42   ` [PATCH v7 10/49] x86emul: support AVX512{F, BW} integer unpack insns Jan Beulich
2018-12-19 14:42   ` [PATCH v7 11/49] x86emul: support AVX512{F, BW, _VBMI} full permute insns Jan Beulich
2018-12-19 14:43   ` [PATCH v7 12/49] x86emul: support AVX512{F, BW} integer shuffle insns Jan Beulich
2018-12-19 14:43   ` [PATCH v7 13/49] x86emul: support AVX512{BW, DQ} mask move insns Jan Beulich
2018-12-19 14:44   ` [PATCH v7 14/49] x86emul: basic AVX512BW testing Jan Beulich
2018-12-19 14:46   ` [PATCH v7 15/49] x86emul: basic AVX512DQ testing Jan Beulich
2018-12-19 14:46   ` [PATCH v7 16/49] x86emul: support AVX512F move high/low insns Jan Beulich
2018-12-19 14:47   ` [PATCH v7 17/49] x86emul: support AVX512F move duplicate insns Jan Beulich
2018-12-19 14:47   ` [PATCH v7 18/49] x86emul: support AVX512{F, BW, _VBMI} permute insns Jan Beulich
2018-12-19 14:48   ` [PATCH v7 19/49] x86emul: support AVX512BW pack insns Jan Beulich
2018-12-19 14:48   ` [PATCH v7 20/49] x86emul: support AVX512F floating-point conversion insns Jan Beulich
2018-12-19 14:48   ` [PATCH v7 21/49] x86emul: support AVX512F legacy-equivalent packed int/FP " Jan Beulich
2018-12-19 14:51   ` [PATCH v7 22/49] x86emul: support AVX512F legacy-equivalent scalar " Jan Beulich
2018-12-19 14:51   ` [PATCH v7 23/49] x86emul: support AVX512DQ packed quad-int/FP " Jan Beulich
2018-12-19 14:52   ` [PATCH v7 24/49] x86emul: support AVX512{F, DQ} uint-to-FP " Jan Beulich
2018-12-19 14:52   ` [PATCH v7 25/49] x86emul: support AVX512{F, DQ} FP-to-uint " Jan Beulich
2018-12-19 14:53   ` [PATCH v7 26/49] x86emul: support remaining AVX512F legacy-equivalent insns Jan Beulich
2018-12-19 14:53   ` [PATCH v7 27/49] x86emul: support remaining AVX512BW " Jan Beulich
2018-12-19 14:54   ` [PATCH v7 28/49] x86emul: support AVX512{F, ER} reciprocal insns Jan Beulich
2018-12-19 14:55   ` [PATCH v7 29/49] x86emul: support AVX512F floating point manipulation insns Jan Beulich
2018-12-19 14:55   ` [PATCH v7 30/49] x86emul: support AVX512DQ " Jan Beulich
2018-12-19 14:56   ` [PATCH v7 31/49] x86emul: support AVX512{F, _VBMI2} compress/expand insns Jan Beulich
2018-12-19 14:56   ` [PATCH v7 32/49] x86emul: support remaining misc AVX512{F, BW} insns Jan Beulich
2018-12-19 14:57   ` [PATCH v7 33/49] x86emul: support AVX512F gather insns Jan Beulich
2018-12-19 14:57   ` [PATCH v7 34/49] x86emul: add high register S/G test cases Jan Beulich
2018-12-19 14:58   ` [PATCH v7 35/49] x86emul: support AVX512F scatter insns Jan Beulich
2018-12-19 14:59   ` [PATCH v7 36/49] x86emul: support AVX512PF insns Jan Beulich
2018-12-19 14:59   ` [PATCH v7 37/49] x86emul: support AVX512CD insns Jan Beulich
2018-12-19 15:00   ` [PATCH v7 38/49] x86emul: complete support of AVX512_VBMI insns Jan Beulich
2018-12-19 15:00   ` [PATCH v7 39/49] x86emul: support of AVX512* population count insns Jan Beulich
2018-12-19 15:01   ` [PATCH v7 40/49] x86emul: support of AVX512_IFMA insns Jan Beulich
2018-12-19 15:01   ` [PATCH v7 42/49] x86emul: support remaining AVX512_VBMI2 insns Jan Beulich
2018-12-19 15:02   ` [PATCH v7 42/49] x86emul: support AVX512_4FMAPS insns Jan Beulich
2018-12-19 15:05   ` [PATCH v7 43/49] x86emul: support AVX512_4VNNIW insns Jan Beulich
2018-12-19 15:06   ` [PATCH v7 44/49] x86emul: support AVX512_VNNI insns Jan Beulich
2018-12-19 15:06   ` [PATCH v7 45/49] x86emul: support VPCLMULQDQ insns Jan Beulich
2018-12-19 15:07   ` [PATCH v7 46/49] x86emul: support VAES insns Jan Beulich
2018-12-19 15:07   ` [PATCH v7 47/49] x86emul: support GFNI insns Jan Beulich
2018-12-19 15:07   ` [PATCH v7 48/49] x86emul: restore ordering within main switch statement Jan Beulich
2018-12-19 15:08   ` [PATCH v7 49/49] tools: re-sync CPUID leaf 7 tables Jan Beulich
2019-03-14 11:07     ` Andrew Cooper
2019-03-15 10:30 ` [PATCH v8 00/50] x86emul: remaining AVX512 support Jan Beulich
2019-03-15 10:36   ` [PATCH v8 01/50] x86emul: no need to set fault_suppression to false for VMOVNT* Jan Beulich
2019-03-15 16:52     ` Andrew Cooper
2019-03-15 10:36   ` [PATCH v8 02/50] x86emul: support AVX512{F, BW, DQ} extract insns Jan Beulich
2019-03-15 17:51     ` Andrew Cooper
2019-03-15 10:37   ` [PATCH v8 03/50] x86emul: support AVX512{F, BW, DQ} insert insns Jan Beulich
2019-03-15 10:38   ` [PATCH v8 04/50] x86emul: basic AVX512F testing Jan Beulich
2019-03-15 10:39   ` [PATCH v8 05/50] x86emul: support AVX512{F, BW, DQ} integer broadcast insns Jan Beulich
2019-03-15 10:39   ` [PATCH v8 06/50] x86emul: basic AVX512VL testing Jan Beulich
2019-03-15 10:40   ` [PATCH v8 07/50] x86emul: support AVX512{F, BW} zero- and sign-extending moves Jan Beulich
2019-03-15 18:02     ` Andrew Cooper
2019-03-15 10:40   ` [PATCH v8 08/50] x86emul: support AVX512{F, BW} down conversion moves Jan Beulich
2019-03-15 18:10     ` Andrew Cooper
2019-03-15 10:41   ` [PATCH v8 09/50] x86emul: support AVX512{F, BW} integer unpack insns Jan Beulich
2019-03-15 18:21     ` Andrew Cooper
2019-03-18  9:55       ` Jan Beulich
2019-05-20 12:11         ` Andrew Cooper
2019-05-20 12:11           ` [Xen-devel] " Andrew Cooper
2019-03-15 10:41   ` [PATCH v8 10/50] x86emul: support AVX512{F, BW, _VBMI} full permute insns Jan Beulich
2019-05-17 16:50     ` Andrew Cooper
2019-05-17 16:50       ` [Xen-devel] " Andrew Cooper
2019-05-20  6:55       ` Jan Beulich
2019-05-20  6:55         ` [Xen-devel] " Jan Beulich
2019-05-20 12:10         ` Andrew Cooper
2019-05-20 12:10           ` [Xen-devel] " Andrew Cooper
2019-03-15 10:43   ` [PATCH v8 11/50] x86emul: support AVX512{F, BW} integer shuffle insns Jan Beulich
2019-05-17 17:01     ` Andrew Cooper
2019-05-17 17:01       ` [Xen-devel] " Andrew Cooper
2019-03-15 10:43   ` [PATCH v8 12/50] x86emul: support AVX512{BW, DQ} mask move insns Jan Beulich
2019-05-17 17:02     ` Andrew Cooper
2019-05-17 17:02       ` [Xen-devel] " Andrew Cooper
2019-03-15 10:43   ` [PATCH v8 13/50] x86emul: basic AVX512BW testing Jan Beulich
2019-05-17 17:03     ` Andrew Cooper
2019-05-17 17:03       ` [Xen-devel] " Andrew Cooper
2019-03-15 10:44   ` [PATCH v8 14/50] x86emul: basic AVX512DQ testing Jan Beulich
2019-05-17 17:03     ` Andrew Cooper
2019-05-17 17:03       ` [Xen-devel] " Andrew Cooper
2019-03-15 10:44   ` [PATCH v8 15/50] x86emul: support AVX512F move high/low insns Jan Beulich
2019-05-21 10:59     ` Andrew Cooper
2019-05-21 10:59       ` [Xen-devel] " Andrew Cooper
2019-03-15 10:45   ` [PATCH v8 16/50] x86emul: support AVX512F move duplicate insns Jan Beulich
2019-05-21 11:09     ` Andrew Cooper
2019-05-21 11:09       ` [Xen-devel] " Andrew Cooper
2019-03-15 10:46   ` [PATCH v8 17/50] x86emul: support AVX512{F, BW, _VBMI} permute insns Jan Beulich
2019-05-21 11:24     ` Andrew Cooper
2019-05-21 11:24       ` [Xen-devel] " Andrew Cooper
2019-03-15 10:46   ` [PATCH v8 18/50] x86emul: support AVX512BW pack insns Jan Beulich
2019-05-21 11:26     ` Andrew Cooper
2019-05-21 11:26       ` [Xen-devel] " Andrew Cooper
2019-03-15 10:47   ` [PATCH v8 19/50] x86emul: support AVX512F floating-point conversion insns Jan Beulich
2019-05-21 11:33     ` Andrew Cooper
2019-05-21 11:33       ` [Xen-devel] " Andrew Cooper
2019-05-21 15:46       ` Jan Beulich
2019-05-21 15:46         ` [Xen-devel] " Jan Beulich
2019-05-23 16:08         ` Andrew Cooper
2019-05-23 16:08           ` [Xen-devel] " Andrew Cooper
2019-03-15 10:47   ` [PATCH v8 20/50] x86emul: support AVX512F legacy-equivalent packed int/FP " Jan Beulich
2019-05-21 11:37     ` Andrew Cooper
2019-05-21 11:37       ` [Xen-devel] " Andrew Cooper
2019-03-15 10:52   ` [PATCH v8 21/50] x86emul: support AVX512F legacy-equivalent scalar " Jan Beulich
2019-05-21 11:44     ` Andrew Cooper
2019-05-21 11:44       ` [Xen-devel] " Andrew Cooper
2019-03-15 10:52   ` [PATCH v8 22/50] x86emul: support AVX512DQ packed quad-int/FP " Jan Beulich
2019-05-21 11:53     ` Andrew Cooper
2019-05-21 11:53       ` [Xen-devel] " Andrew Cooper
2019-03-15 10:53   ` [PATCH v8 23/50] x86emul: support AVX512{F, DQ} uint-to-FP " Jan Beulich
2019-05-21 11:58     ` Andrew Cooper
2019-05-21 11:58       ` [Xen-devel] " Andrew Cooper
2019-03-15 10:54   ` [PATCH v8 24/50] x86emul: support AVX512{F, DQ} FP-to-uint " Jan Beulich
2019-05-21 12:09     ` Andrew Cooper
2019-05-21 12:09       ` [Xen-devel] " Andrew Cooper
2019-03-15 10:54   ` [PATCH v8 25/50] x86emul: support remaining AVX512F legacy-equivalent insns Jan Beulich
2019-05-21 13:06     ` Andrew Cooper
2019-05-21 13:06       ` [Xen-devel] " Andrew Cooper
2019-03-15 10:54   ` [PATCH v8 26/50] x86emul: support remaining AVX512BW " Jan Beulich
2019-05-21 13:08     ` Andrew Cooper
2019-05-21 13:08       ` [Xen-devel] " Andrew Cooper
2019-05-21 13:34       ` Jan Beulich
2019-05-21 13:34         ` [Xen-devel] " Jan Beulich
2019-05-23 16:10     ` Andrew Cooper
2019-05-23 16:10       ` [Xen-devel] " Andrew Cooper
2019-03-15 10:55   ` [PATCH v8 27/50] x86emul: support AVX512{F, ER} reciprocal insns Jan Beulich
2019-05-23 16:15     ` Andrew Cooper
2019-05-23 16:15       ` [Xen-devel] " Andrew Cooper
2019-05-24  6:43       ` Jan Beulich
2019-05-24  6:43         ` [Xen-devel] " Jan Beulich
2019-05-24 20:48         ` Andrew Cooper
2019-05-24 20:48           ` [Xen-devel] " Andrew Cooper
2019-05-27  8:02           ` Jan Beulich
2019-05-27  8:02             ` [Xen-devel] " Jan Beulich
2019-05-29 10:00             ` Andrew Cooper
2019-05-29 10:00               ` [Xen-devel] " Andrew Cooper
2019-03-15 10:56   ` [PATCH v8 28/50] x86emul: support AVX512F floating point manipulation insns Jan Beulich
2019-05-29 12:51     ` Andrew Cooper
2019-05-29 12:51       ` [Xen-devel] " Andrew Cooper
2019-05-29 13:15       ` Jan Beulich
2019-05-29 13:15         ` [Xen-devel] " Jan Beulich
2019-06-10 14:01         ` Andrew Cooper
2019-06-10 14:03     ` Andrew Cooper
2019-03-15 10:56   ` [PATCH v8 29/50] x86emul: support AVX512DQ " Jan Beulich
2019-06-10 14:06     ` [Xen-devel] " Andrew Cooper
2019-03-15 10:56   ` [PATCH v8 30/50] x86emul: support AVX512{F, _VBMI2} compress/expand insns Jan Beulich
2019-06-10 14:51     ` [Xen-devel] " Andrew Cooper
2019-06-11 10:20       ` Jan Beulich
2019-06-18 16:24         ` Andrew Cooper
2019-06-19  6:38           ` Jan Beulich
2019-03-15 10:58   ` [PATCH v8 31/50] x86emul: support remaining misc AVX512{F, BW} insns Jan Beulich
2019-06-18 16:42     ` [Xen-devel] " Andrew Cooper
2019-06-19  6:44       ` Jan Beulich
2019-03-15 10:58   ` [PATCH v8 32/50] x86emul: support AVX512F gather insns Jan Beulich
2019-06-19 12:05     ` [Xen-devel] " Andrew Cooper
2019-06-19 12:43       ` Jan Beulich
2019-03-15 10:59   ` [PATCH v8 33/50] x86emul: add high register S/G test cases Jan Beulich
2019-06-19 12:07     ` [Xen-devel] " Andrew Cooper
2019-03-15 10:59   ` [PATCH v8 34/50] x86emul: support AVX512F scatter insns Jan Beulich
2019-03-15 11:00   ` [PATCH v8 35/50] x86emul: support AVX512PF insns Jan Beulich
2019-03-15 11:00   ` [PATCH v8 36/50] x86emul: support AVX512CD insns Jan Beulich
2019-06-19 12:13     ` [Xen-devel] " Andrew Cooper
2019-03-15 11:01   ` [PATCH v8 37/50] x86emul: complete support of AVX512_VBMI insns Jan Beulich
2019-06-19 12:16     ` [Xen-devel] " Andrew Cooper
2019-03-15 11:01   ` [PATCH v8 38/50] x86emul: support of AVX512* population count insns Jan Beulich
2019-06-19 12:22     ` [Xen-devel] " Andrew Cooper
2019-06-19 12:48       ` Jan Beulich
2019-03-15 11:02   ` [PATCH v8 39/50] x86emul: support of AVX512_IFMA insns Jan Beulich
2019-06-19 12:23     ` [Xen-devel] " Andrew Cooper
2019-03-15 11:02   ` [PATCH v8 40/50] x86emul: support remaining AVX512_VBMI2 insns Jan Beulich
2019-06-19 12:25     ` [Xen-devel] " Andrew Cooper
2019-03-15 11:04   ` [PATCH v8 41/50] x86emul: support AVX512_4FMAPS insns Jan Beulich
2019-06-19 14:58     ` [Xen-devel] " Andrew Cooper
2019-06-21  6:50       ` Jan Beulich
2019-03-15 11:04   ` [PATCH v8 42/50] x86emul: support AVX512_4VNNIW insns Jan Beulich
2019-06-19 14:58     ` [Xen-devel] " Andrew Cooper
2019-03-15 11:04   ` [PATCH v8 43/50] x86emul: support AVX512_VNNI insns Jan Beulich
2019-06-19 15:01     ` [Xen-devel] " Andrew Cooper
2019-06-21  6:55       ` Jan Beulich
2019-03-15 11:05   ` [PATCH v8 44/50] x86emul: support VPCLMULQDQ insns Jan Beulich
2019-06-21 12:52     ` [Xen-devel] " Andrew Cooper
2019-06-21 13:44       ` Jan Beulich
2019-03-15 11:06   ` [PATCH v8 45/50] x86emul: support VAES insns Jan Beulich
2019-06-21 12:57     ` [Xen-devel] " Andrew Cooper
2019-03-15 11:06   ` [PATCH v8 46/50] x86emul: support GFNI insns Jan Beulich
2019-06-21 13:19     ` [Xen-devel] " Andrew Cooper
2019-06-21 13:33       ` Andrew Cooper
2019-06-21 14:00       ` Jan Beulich
2019-06-21 14:20         ` Andrew Cooper
2019-06-21 15:02           ` Jan Beulich
2019-06-25  6:48           ` Jan Beulich
2019-03-15 11:07   ` [PATCH v8 47/50] x86emul: restore ordering within main switch statement Jan Beulich
2019-06-21 13:20     ` [Xen-devel] " Andrew Cooper
2019-03-15 11:07   ` [PATCH v8 48/50] x86emul: add an AES/VAES test case to the harness Jan Beulich
2019-06-21 13:36     ` [Xen-devel] " Andrew Cooper
2019-06-21 14:04       ` Jan Beulich
2019-06-21 14:20         ` Andrew Cooper
2019-03-15 11:08   ` Jan Beulich [this message]
2019-06-21 13:51     ` [Xen-devel] [PATCH v8 49/50] x86emul: add a SHA " Andrew Cooper
2019-06-21 14:10       ` Jan Beulich
2019-06-21 14:23         ` Andrew Cooper
2019-03-15 11:08   ` [PATCH v8 50/50] x86emul: add a PCLMUL/VPCLMUL " Jan Beulich
2019-06-21 13:58     ` [Xen-devel] " Andrew Cooper

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