From: "Jan Beulich" <JBeulich@suse.com>
To: "Andrew Cooper" <andrew.cooper3@citrix.com>
Cc: xen-devel <xen-devel@lists.xenproject.org>, WeiLiu <wl@xen.org>,
Roger Pau Monne <roger.pau@citrix.com>
Subject: Re: [Xen-devel] [PATCH] x86/x2APIC: tighten check in cluster mode IPI sending
Date: Thu, 13 Jun 2019 07:21:39 -0600 [thread overview]
Message-ID: <5D024DE30200007800237DFA@prv1-mh.provo.novell.com> (raw)
In-Reply-To: <9172f488-93e5-1fe8-d5b1-dedb53af4667@citrix.com>
>>> On 13.06.19 at 15:11, <andrew.cooper3@citrix.com> wrote:
> On 13/06/2019 14:06, Jan Beulich wrote:
>> It is only of limited use to check the full accumulated 32-bit value,
>> because the high halves are the cluster ID. What needs to be non-zero is
>> the bit map at the bottom, or else APIC errors will result.
>>
>> Signed-off-by: Jan Beulich <jbeulich@suse.com>
>
> I take it you located the the source of the APIC errors.
Yes, albeit the change here is just a result of me guessing where they
might have come from, i.e. it wasn't the IPI sending in the end. Instead
there was one issue each with losing part or all of the 32-bit destination
in both the I/O-APIC RTE and the MSI message massaging functions.
IOW things would also not have worked correctly in physical mode with
more than 256 CPUs (or fewer, with discontiguous physical APIC IDs).
> I can't find anything in the manual which explicitly states that APIC
> errors will arrive, but 10.12.10.2 does clearly identify that a logical
> x2APIC ID is non-zero in its bottom 16 bits.
>
> Reviewed-by: Andrew Cooper <andrew.cooper3@citrix.com>
Thanks.
Jan
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prev parent reply other threads:[~2019-06-13 13:22 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-06-13 13:06 [Xen-devel] [PATCH] x86/x2APIC: tighten check in cluster mode IPI sending Jan Beulich
2019-06-13 13:11 ` Andrew Cooper
2019-06-13 13:21 ` Jan Beulich [this message]
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