[PATCH v2 0/2] x86/AMD: correct certain Fam17 checks

[PATCH v2 0/2] x86/AMD: correct certain Fam17 checks

[Jan Beulich]

1: correct certain Fam17 checks
2: limit C1E disable family range

v2: Follow Andrew's suggestion for NB_CFG in patch 1. New patch 2.

Jan



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[Xen-devel] [PATCH v2 0/2] x86/AMD: correct certain Fam17 checks

[Jan Beulich]

1: correct certain Fam17 checks
2: limit C1E disable family range

v2: Follow Andrew's suggestion for NB_CFG in patch 1. New patch 2.

Jan



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[PATCH v2 1/2] x86/AMD: correct certain Fam17 checks

[Jan Beulich]

Commit 3157bb4e13 ("Add MSR support for various feature AMD processor
families") converted certain checks for Fam11 to include families all
the way up to Fam17. The commit having no description, it is hard to
tell whether this was a mechanical dec->hex conversion mistake, or
indeed intended. In any event the NB_CFG handling needs to be restricted
to Fam16 and below: Fam17 doesn't really have such an MSR anymore. As
per observation it's read-zero / write-discard now, so make PV uniformly
(with the exception of pinned Dom0 vCPU-s) behave so, just like HVM
already does.

Mirror the NB_CFG behavior to MSR_FAM10H_MMIO_CONF_BASE as well, except
that here the vendor/model check is kept in place (for now at least).

A non-MMCFG extended config space access mechanism still appears to
exist, but code to deal with it will need to be written down the road,
when it can actually be tested.

Reported-by: Pu Wen <puwen@hygon.cn>
Signed-off-by: Jan Beulich <jbeulich@suse.com>
---
v2: Make NB_CFG read-zero / write-discard for PV DomU, just like HVM has
    it already. I've not applied "In principle, Acked-by: Andrew Cooper
    <andrew.cooper3@citrix.com>".

--- a/xen/arch/x86/hvm/ioreq.c
+++ b/xen/arch/x86/hvm/ioreq.c
@@ -1288,7 +1288,7 @@ struct hvm_ioreq_server *hvm_select_iore
              d->arch.cpuid->x86_vendor == X86_VENDOR_AMD &&
              (x86_fam = get_cpu_family(
                  d->arch.cpuid->basic.raw_fms, NULL, NULL)) > 0x10 &&
-             x86_fam <= 0x17 )
+             x86_fam < 0x17 )
         {
             uint64_t msr_val;
 
--- a/xen/arch/x86/pv/emul-priv-op.c
+++ b/xen/arch/x86/pv/emul-priv-op.c
@@ -195,7 +195,7 @@ static bool pci_cfg_ok(struct domain *cu
     /* AMD extended configuration space access? */
     if ( CF8_ADDR_HI(currd->arch.pci_cf8) &&
          boot_cpu_data.x86_vendor == X86_VENDOR_AMD &&
-         boot_cpu_data.x86 >= 0x10 && boot_cpu_data.x86 <= 0x17 )
+         boot_cpu_data.x86 >= 0x10 && boot_cpu_data.x86 < 0x17 )
     {
         uint64_t msr_val;
 
@@ -893,6 +893,17 @@ static int read_msr(unsigned int reg, ui
         *val = 0;
         return X86EMUL_OKAY;
 
+    case MSR_FAM10H_MMIO_CONF_BASE:
+        if ( boot_cpu_data.x86_vendor != X86_VENDOR_AMD ||
+             boot_cpu_data.x86 < 0x10 || boot_cpu_data.x86 >= 0x17 )
+            break;
+        /* fall through */
+    case MSR_AMD64_NB_CFG:
+        if ( is_hwdom_pinned_vcpu(curr) )
+            goto normal;
+        *val = 0;
+        return X86EMUL_OKAY;
+
     case MSR_IA32_MISC_ENABLE:
         rdmsrl(reg, *val);
         *val = guest_misc_enable(*val);
@@ -1003,9 +1014,6 @@ static int write_msr(unsigned int reg, u
         break;
 
     case MSR_AMD64_NB_CFG:
-        if ( boot_cpu_data.x86_vendor != X86_VENDOR_AMD ||
-             boot_cpu_data.x86 < 0x10 || boot_cpu_data.x86 > 0x17 )
-            break;
         if ( !is_hwdom_pinned_vcpu(curr) )
             return X86EMUL_OKAY;
         if ( (rdmsr_safe(MSR_AMD64_NB_CFG, temp) != 0) ||
@@ -1017,7 +1025,7 @@ static int write_msr(unsigned int reg, u
 
     case MSR_FAM10H_MMIO_CONF_BASE:
         if ( boot_cpu_data.x86_vendor != X86_VENDOR_AMD ||
-             boot_cpu_data.x86 < 0x10 || boot_cpu_data.x86 > 0x17 )
+             boot_cpu_data.x86 < 0x10 || boot_cpu_data.x86 >= 0x17 )
             break;
         if ( !is_hwdom_pinned_vcpu(curr) )
             return X86EMUL_OKAY;





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[Xen-devel] [PATCH v2 1/2] x86/AMD: correct certain Fam17 checks

[Jan Beulich]

Commit 3157bb4e13 ("Add MSR support for various feature AMD processor
families") converted certain checks for Fam11 to include families all
the way up to Fam17. The commit having no description, it is hard to
tell whether this was a mechanical dec->hex conversion mistake, or
indeed intended. In any event the NB_CFG handling needs to be restricted
to Fam16 and below: Fam17 doesn't really have such an MSR anymore. As
per observation it's read-zero / write-discard now, so make PV uniformly
(with the exception of pinned Dom0 vCPU-s) behave so, just like HVM
already does.

Mirror the NB_CFG behavior to MSR_FAM10H_MMIO_CONF_BASE as well, except
that here the vendor/model check is kept in place (for now at least).

A non-MMCFG extended config space access mechanism still appears to
exist, but code to deal with it will need to be written down the road,
when it can actually be tested.

Reported-by: Pu Wen <puwen@hygon.cn>
Signed-off-by: Jan Beulich <jbeulich@suse.com>
---
v2: Make NB_CFG read-zero / write-discard for PV DomU, just like HVM has
    it already. I've not applied "In principle, Acked-by: Andrew Cooper
    <andrew.cooper3@citrix.com>".

--- a/xen/arch/x86/hvm/ioreq.c
+++ b/xen/arch/x86/hvm/ioreq.c
@@ -1288,7 +1288,7 @@ struct hvm_ioreq_server *hvm_select_iore
              d->arch.cpuid->x86_vendor == X86_VENDOR_AMD &&
              (x86_fam = get_cpu_family(
                  d->arch.cpuid->basic.raw_fms, NULL, NULL)) > 0x10 &&
-             x86_fam <= 0x17 )
+             x86_fam < 0x17 )
         {
             uint64_t msr_val;
 
--- a/xen/arch/x86/pv/emul-priv-op.c
+++ b/xen/arch/x86/pv/emul-priv-op.c
@@ -195,7 +195,7 @@ static bool pci_cfg_ok(struct domain *cu
     /* AMD extended configuration space access? */
     if ( CF8_ADDR_HI(currd->arch.pci_cf8) &&
          boot_cpu_data.x86_vendor == X86_VENDOR_AMD &&
-         boot_cpu_data.x86 >= 0x10 && boot_cpu_data.x86 <= 0x17 )
+         boot_cpu_data.x86 >= 0x10 && boot_cpu_data.x86 < 0x17 )
     {
         uint64_t msr_val;
 
@@ -893,6 +893,17 @@ static int read_msr(unsigned int reg, ui
         *val = 0;
         return X86EMUL_OKAY;
 
+    case MSR_FAM10H_MMIO_CONF_BASE:
+        if ( boot_cpu_data.x86_vendor != X86_VENDOR_AMD ||
+             boot_cpu_data.x86 < 0x10 || boot_cpu_data.x86 >= 0x17 )
+            break;
+        /* fall through */
+    case MSR_AMD64_NB_CFG:
+        if ( is_hwdom_pinned_vcpu(curr) )
+            goto normal;
+        *val = 0;
+        return X86EMUL_OKAY;
+
     case MSR_IA32_MISC_ENABLE:
         rdmsrl(reg, *val);
         *val = guest_misc_enable(*val);
@@ -1003,9 +1014,6 @@ static int write_msr(unsigned int reg, u
         break;
 
     case MSR_AMD64_NB_CFG:
-        if ( boot_cpu_data.x86_vendor != X86_VENDOR_AMD ||
-             boot_cpu_data.x86 < 0x10 || boot_cpu_data.x86 > 0x17 )
-            break;
         if ( !is_hwdom_pinned_vcpu(curr) )
             return X86EMUL_OKAY;
         if ( (rdmsr_safe(MSR_AMD64_NB_CFG, temp) != 0) ||
@@ -1017,7 +1025,7 @@ static int write_msr(unsigned int reg, u
 
     case MSR_FAM10H_MMIO_CONF_BASE:
         if ( boot_cpu_data.x86_vendor != X86_VENDOR_AMD ||
-             boot_cpu_data.x86 < 0x10 || boot_cpu_data.x86 > 0x17 )
+             boot_cpu_data.x86 < 0x10 || boot_cpu_data.x86 >= 0x17 )
             break;
         if ( !is_hwdom_pinned_vcpu(curr) )
             return X86EMUL_OKAY;





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[PATCH v2 2/2] x86/AMD: limit C1E disable family range

[Jan Beulich]

Just like for other family values of 0x17 (see "x86/AMD: correct certain
Fam17 checks"), commit 3157bb4e13 ("Add MSR support for various feature
AMD processor families") made the original check for Fam11 here include
families all the way up to Fam17. The involved MSR (0xC0010055),
however, is fully reserved starting from Fam16, and the two bits of
interest are reserved for Fam12 and onwards (albeit I admit I wasn't
able to find any Fam13 doc). Restore the upper bound to be Fam11.

Signed-off-by: Jan Beulich <jbeulich@suse.com>
---
v2: New.

--- a/xen/arch/x86/cpu/amd.c
+++ b/xen/arch/x86/cpu/amd.c
@@ -628,7 +628,7 @@ static void init_amd(struct cpuinfo_x86
 
 	switch(c->x86)
 	{
-	case 0xf ... 0x17:
+	case 0xf ... 0x11:
 		disable_c1e(NULL);
 		if (acpi_smi_cmd && (acpi_enable_value | acpi_disable_value))
 			amd_acpi_c1e_quirk = true;



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[Xen-devel] [PATCH v2 2/2] x86/AMD: limit C1E disable family range

[Jan Beulich]

Just like for other family values of 0x17 (see "x86/AMD: correct certain
Fam17 checks"), commit 3157bb4e13 ("Add MSR support for various feature
AMD processor families") made the original check for Fam11 here include
families all the way up to Fam17. The involved MSR (0xC0010055),
however, is fully reserved starting from Fam16, and the two bits of
interest are reserved for Fam12 and onwards (albeit I admit I wasn't
able to find any Fam13 doc). Restore the upper bound to be Fam11.

Signed-off-by: Jan Beulich <jbeulich@suse.com>
---
v2: New.

--- a/xen/arch/x86/cpu/amd.c
+++ b/xen/arch/x86/cpu/amd.c
@@ -628,7 +628,7 @@ static void init_amd(struct cpuinfo_x86
 
 	switch(c->x86)
 	{
-	case 0xf ... 0x17:
+	case 0xf ... 0x11:
 		disable_c1e(NULL);
 		if (acpi_smi_cmd && (acpi_enable_value | acpi_disable_value))
 			amd_acpi_c1e_quirk = true;



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Ping: [PATCH v2 2/2] x86/AMD: limit C1E disable family range

[Jan Beulich]

>>> On 05.04.19 at 16:27,  wrote:
> Just like for other family values of 0x17 (see "x86/AMD: correct certain
> Fam17 checks"), commit 3157bb4e13 ("Add MSR support for various feature
> AMD processor families") made the original check for Fam11 here include
> families all the way up to Fam17. The involved MSR (0xC0010055),
> however, is fully reserved starting from Fam16, and the two bits of
> interest are reserved for Fam12 and onwards (albeit I admit I wasn't
> able to find any Fam13 doc). Restore the upper bound to be Fam11.
> 
> Signed-off-by: Jan Beulich <jbeulich@suse.com>
> ---
> v2: New.
> 
> --- a/xen/arch/x86/cpu/amd.c
> +++ b/xen/arch/x86/cpu/amd.c
> @@ -628,7 +628,7 @@ static void init_amd(struct cpuinfo_x86
>  
>  	switch(c->x86)
>  	{
> -	case 0xf ... 0x17:
> +	case 0xf ... 0x11:
>  		disable_c1e(NULL);
>  		if (acpi_smi_cmd && (acpi_enable_value | acpi_disable_value))
>  			amd_acpi_c1e_quirk = true;
> 
> 





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[Xen-devel] Ping: [PATCH v2 2/2] x86/AMD: limit C1E disable family range

[Jan Beulich]

>>> On 05.04.19 at 16:27,  wrote:
> Just like for other family values of 0x17 (see "x86/AMD: correct certain
> Fam17 checks"), commit 3157bb4e13 ("Add MSR support for various feature
> AMD processor families") made the original check for Fam11 here include
> families all the way up to Fam17. The involved MSR (0xC0010055),
> however, is fully reserved starting from Fam16, and the two bits of
> interest are reserved for Fam12 and onwards (albeit I admit I wasn't
> able to find any Fam13 doc). Restore the upper bound to be Fam11.
> 
> Signed-off-by: Jan Beulich <jbeulich@suse.com>
> ---
> v2: New.
> 
> --- a/xen/arch/x86/cpu/amd.c
> +++ b/xen/arch/x86/cpu/amd.c
> @@ -628,7 +628,7 @@ static void init_amd(struct cpuinfo_x86
>  
>  	switch(c->x86)
>  	{
> -	case 0xf ... 0x17:
> +	case 0xf ... 0x11:
>  		disable_c1e(NULL);
>  		if (acpi_smi_cmd && (acpi_enable_value | acpi_disable_value))
>  			amd_acpi_c1e_quirk = true;
> 
> 





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[Xen-devel] Ping#2: [PATCH v2 0/2] x86/AMD: correct certain Fam17 checks

[Jan Beulich]

>>> On 05.04.19 at 15:55,  wrote:
> 1: correct certain Fam17 checks
> 2: limit C1E disable family range
> 
> v2: Follow Andrew's suggestion for NB_CFG in patch 1. New patch 2.
> 
> Jan



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Re: [Xen-devel] [PATCH v2 1/2] x86/AMD: correct certain Fam17 checks

[Andrew Cooper]

On 05/04/2019 15:26, Jan Beulich wrote:
> Commit 3157bb4e13 ("Add MSR support for various feature AMD processor
> families") converted certain checks for Fam11 to include families all
> the way up to Fam17. The commit having no description, it is hard to
> tell whether this was a mechanical dec->hex conversion mistake, or
> indeed intended. In any event the NB_CFG handling needs to be restricted
> to Fam16 and below: Fam17 doesn't really have such an MSR anymore. As
> per observation it's read-zero / write-discard now, so make PV uniformly
> (with the exception of pinned Dom0 vCPU-s) behave so, just like HVM
> already does.
>
> Mirror the NB_CFG behavior to MSR_FAM10H_MMIO_CONF_BASE as well, except
> that here the vendor/model check is kept in place (for now at least).
>
> A non-MMCFG extended config space access mechanism still appears to
> exist, but code to deal with it will need to be written down the road,
> when it can actually be tested.
>
> Reported-by: Pu Wen <puwen@hygon.cn>
> Signed-off-by: Jan Beulich <jbeulich@suse.com>
> ---
> v2: Make NB_CFG read-zero / write-discard for PV DomU, just like HVM has
>     it already. I've not applied "In principle, Acked-by: Andrew Cooper
>     <andrew.cooper3@citrix.com>".

I suppose this is slightly better intermediate step.  I guess I'll have
to do the proper fix of removing MSR_AMD64_NB_CFG from the guest
emulation paths, where it absolutely doesn't belong.

Acked-by: Andrew Cooper <andrew.cooper3@citrix.com>

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Re: [Xen-devel] [PATCH v2 2/2] x86/AMD: limit C1E disable family range

[Andrew Cooper]

On 05/04/2019 15:27, Jan Beulich wrote:
> Just like for other family values of 0x17 (see "x86/AMD: correct certain
> Fam17 checks"), commit 3157bb4e13 ("Add MSR support for various feature
> AMD processor families") made the original check for Fam11 here include
> families all the way up to Fam17. The involved MSR (0xC0010055),
> however, is fully reserved starting from Fam16, and the two bits of
> interest are reserved for Fam12 and onwards (albeit I admit I wasn't
> able to find any Fam13 doc). Restore the upper bound to be Fam11.
>
> Signed-off-by: Jan Beulich <jbeulich@suse.com>

Acked-by: Andrew Cooper <andrew.cooper3@citrix.com>

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Re: [Xen-devel] [PATCH v2 1/2] x86/AMD: correct certain Fam17 checks

[Jan Beulich]

>>> On 17.06.19 at 18:00, <andrew.cooper3@citrix.com> wrote:
> On 05/04/2019 15:26, Jan Beulich wrote:
>> Commit 3157bb4e13 ("Add MSR support for various feature AMD processor
>> families") converted certain checks for Fam11 to include families all
>> the way up to Fam17. The commit having no description, it is hard to
>> tell whether this was a mechanical dec->hex conversion mistake, or
>> indeed intended. In any event the NB_CFG handling needs to be restricted
>> to Fam16 and below: Fam17 doesn't really have such an MSR anymore. As
>> per observation it's read-zero / write-discard now, so make PV uniformly
>> (with the exception of pinned Dom0 vCPU-s) behave so, just like HVM
>> already does.
>>
>> Mirror the NB_CFG behavior to MSR_FAM10H_MMIO_CONF_BASE as well, except
>> that here the vendor/model check is kept in place (for now at least).
>>
>> A non-MMCFG extended config space access mechanism still appears to
>> exist, but code to deal with it will need to be written down the road,
>> when it can actually be tested.
>>
>> Reported-by: Pu Wen <puwen@hygon.cn>
>> Signed-off-by: Jan Beulich <jbeulich@suse.com>
>> ---
>> v2: Make NB_CFG read-zero / write-discard for PV DomU, just like HVM has
>>     it already. I've not applied "In principle, Acked-by: Andrew Cooper
>>     <andrew.cooper3@citrix.com>".
> 
> I suppose this is slightly better intermediate step.  I guess I'll have
> to do the proper fix of removing MSR_AMD64_NB_CFG from the guest
> emulation paths, where it absolutely doesn't belong.

Well, I'll be curious to see how you will manage to do this without
breaking Dom0-s actually hitting this path. Or else I guess I would
have done so right here.

> Acked-by: Andrew Cooper <andrew.cooper3@citrix.com>

Thanks!

Jan



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