From: "Jan Beulich" <JBeulich@suse.com>
To: "Brian Woods" <brian.woods@amd.com>
Cc: Andrew Cooper <andrew.cooper3@citrix.com>,
Wei Liu <wei.liu2@citrix.com>,
xen-devel <xen-devel@lists.xenproject.org>,
Roger Pau Monne <roger.pau@citrix.com>
Subject: Re: [Xen-devel] [PATCH 3/5] x86/AMD: make C-state handling independent of Dom0
Date: Fri, 21 Jun 2019 00:37:47 -0600 [thread overview]
Message-ID: <5D0C7B3B0200007800239F12@prv1-mh.provo.novell.com> (raw)
In-Reply-To: <20190619155447.GA20907@amd.com>
>>> On 19.06.19 at 17:54, <Brian.Woods@amd.com> wrote:
> On Wed, Jun 19, 2019 at 12:20:40AM -0600, Jan Beulich wrote:
>> >>> On 18.06.19 at 19:22, <Brian.Woods@amd.com> wrote:
>> > On Tue, Jun 11, 2019 at 06:42:33AM -0600, Jan Beulich wrote:
>> >> >>> On 10.06.19 at 18:28, <andrew.cooper3@citrix.com> wrote:
>> >> > On 23/05/2019 13:18, Jan Beulich wrote:
>> >> >> TBD: Can we set local_apic_timer_c2_ok to true? I can't seem to find any
>> >> >> statement in the BKDG / PPR as to whether the LAPIC timer continues
>> >> >> running in CC6.
>> >> >
>> >> > This ought to be easy to determine. Given the description of CC6
>> >> > flushing the cache and power gating the core, I'd say there is a
>> >> > reasonable chance that the LAPIC timer stops in CC6.
>> >>
>> >> But "reasonable chance" isn't enough for my taste here. And from
>> >> what you deduce, the answer to the question would be "no", and
>> >> hence simply no change to be made anywhere. (I do think though
>> >> that it's more complicated than this, because iirc much also depends
>> >> on what the firmware actually does.)
>> >
>> > The LAPIC timer never stops on the currently platforms (Naples and
>> > Rome). This is a knowledgable HW engineer so.
>>
>> Thanks - I've taken note to set the variable accordingly then.
>>
>> >> >> TBD: We may want to verify that HLT indeed is configured to enter CC6.
>> >> >
>> >> > I can't actually spot anything which talks about HLT directly. The
>> >> > closest I can post is CFOH (cache flush on halt) which is an
>> >> > auto-transition from CC1 to CC6 after a specific timeout, but the
>> >> > wording suggests that mwait would also take this path.
>> >>
>> >> Well, I had come across a section describing how HLT can be
>> >> configured to be the same action as the I/O port read from one
>> >> of the three ports involved in C-state management
>> >> (CStateBaseAddr+0...2). But I can't seem to find this again.
>> >>
>> >> As to MWAIT behaving the same, I don't think I can spot proof
>> >> of your interpretation or proof of Brian's.
>> >
>> > It's not really documented clearly. I got my information from the HW
>> > engineers. I've already posted what information I know so I won't
>> > repeat it.
>>
>> At least a pointer to where you had stated this would have been
>> nice. Iirc there's no promotion into CC6 in that case, in contrast
>> to Andrew's reading of the doc.
>
> &mwait_v1_patchset
Hmm, I've looked through the patch descriptions there again, but I
can't find any explicit statement to the effect of there being no
promotion into deeper states when using MWAIT.
Jan
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next prev parent reply other threads:[~2019-06-21 6:38 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-05-23 12:06 [PATCH 0/5] x86: CPU idle management adjustments Jan Beulich
2019-05-23 12:06 ` [Xen-devel] " Jan Beulich
2019-05-23 12:16 ` [PATCH 1/5] x86/cpuidle: switch to uniform meaning of "max_cstate=" Jan Beulich
2019-05-23 12:16 ` [Xen-devel] " Jan Beulich
2019-06-10 15:48 ` Andrew Cooper
2019-06-11 12:13 ` Jan Beulich
2019-05-23 12:17 ` [PATCH 2/5] x86/cpuidle: really use C1 for "urgent" CPUs Jan Beulich
2019-05-23 12:17 ` [Xen-devel] " Jan Beulich
2019-06-10 15:50 ` Andrew Cooper
2019-05-23 12:18 ` [PATCH 3/5] x86/AMD: make C-state handling independent of Dom0 Jan Beulich
2019-05-23 12:18 ` [Xen-devel] " Jan Beulich
2019-06-10 16:28 ` Andrew Cooper
2019-06-11 12:42 ` Jan Beulich
2019-06-18 17:22 ` Woods, Brian
2019-06-19 6:20 ` Jan Beulich
2019-06-19 15:54 ` Woods, Brian
2019-06-21 6:37 ` Jan Beulich [this message]
2019-06-21 14:29 ` Woods, Brian
2019-06-21 14:56 ` Jan Beulich
2019-06-21 15:26 ` Woods, Brian
2019-05-23 12:18 ` [PATCH 4/5] x86: allow limiting the max C-state sub-state Jan Beulich
2019-05-23 12:18 ` [Xen-devel] " Jan Beulich
2019-06-10 16:43 ` Andrew Cooper
2019-06-11 12:46 ` Jan Beulich
2019-05-23 12:19 ` [PATCH 5/5] tools/libxc: allow controlling " Jan Beulich
2019-05-23 12:19 ` [Xen-devel] " Jan Beulich
2019-05-24 14:00 ` Wei Liu
2019-05-24 14:00 ` [Xen-devel] " Wei Liu
2019-06-10 16:54 ` Andrew Cooper
2019-06-11 12:50 ` Jan Beulich
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