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Tue, 16 Jun 2020 19:47:07 +0200 (CEST) Received: from belindir.nask.net.pl (belindir.nask.net.pl [172.16.10.10]) by belindir.nask.net.pl (Postfix) with ESMTP id C54C62171F; Tue, 16 Jun 2020 19:47:07 +0200 (CEST) Date: Tue, 16 Jun 2020 19:47:07 +0200 (CEST) From: =?utf-8?Q?Micha=C5=82_Leszczy=C5=84ski?= To: Roger Pau =?utf-8?Q?Monn=C3=A9?= Message-ID: <676696113.8782412.1592329627666.JavaMail.zimbra@cert.pl> In-Reply-To: <20200616173857.GU735@Air-de-Roger> References: <1548605014.8764792.1592320576239.JavaMail.zimbra@cert.pl> <317430261.8766476.1592321051337.JavaMail.zimbra@cert.pl> <20200616173857.GU735@Air-de-Roger> Subject: Re: [PATCH v1 7/7] x86/vmx: switch IPT MSRs on vmentry/vmexit MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [172.16.10.10] X-Mailer: Zimbra 8.6.0_GA_1194 (ZimbraWebClient - GC83 (Win)/8.6.0_GA_1194) Thread-Topic: x86/vmx: switch IPT MSRs on vmentry/vmexit Thread-Index: IsFlRe2+pVIoLpVn5usOa8NJmss1gw== X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Kevin Tian , Jun Nakajima , Wei Liu , Andrew Cooper , Jan Beulich , Xen-devel Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" ----- 16 cze 2020 o 19:38, Roger Pau Monn=C3=A9 roger.pau@citrix.com napisa= =C5=82(a): > On Tue, Jun 16, 2020 at 05:24:11PM +0200, Micha=C5=82 Leszczy=C5=84ski wr= ote: >> Enable IPT when entering the VM and disable it on vmexit. >> Register state is persisted using vCPU ipt_state structure. >=20 > Shouldn't this be better done using Intel MSR load lists? >=20 > That seems to be what the SDM recommends for tracing VM events. >=20 > Thanks, Roger. This is intentional, additionally described by the comment: // MSR_IA32_RTIT_CTL is context-switched manually instead of being // stored inside VMCS, as of Q2'20 only the most recent processors // support such field in VMCS There is a special feature flag which indicates whether MSR_IA32_RTIT_CTL c= an be loaded using MR load lists. During my experiments, I haven't found an= y single CPU available to me that would declare such a feature flag. I was = mostly testing CPUs that were launched in 2018, so I suppose that this feat= ure is present only on very recent hardware. Unfortunately it's not possibl= e to check on Intel ARK as this information is not listed there at all. Best regards, Micha=C5=82 Leszczy=C5=84ski CERT Polska