[Xen-devel] [PATCH for-4.13 v2 0/2] x86/ioapic: fix clear_IO_APIC_pin when using interrupt remapping

[Xen-devel] [PATCH for-4.13 v2 0/2] x86/ioapic: fix clear_IO_APIC_pin when using interrupt remapping

[Roger Pau Monne]

Hello,

Current code in clear_IO_APIC_pin doesn't properly deal with IO-APIC
entries already configured to point to entries in the iommu interrupt
remapping table, fix this.

Roger Pau Monne (2):
  x86/ioapic: remove usage of TRUE and FALSE in clear_IO_APIC_pin
  x86/ioapic: fix clear_IO_APIC_pin write of raw entries

 xen/arch/x86/io_apic.c | 13 +++++++------
 1 file changed, 7 insertions(+), 6 deletions(-)

-- 
2.23.0


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[Xen-devel] [PATCH for-4.13 v2 1/2] x86/ioapic: remove usage of TRUE and FALSE in clear_IO_APIC_pin

[Roger Pau Monne]

And instead use proper booleans. No functional change intended.

Signed-off-by: Roger Pau Monné <roger.pau@citrix.com>
Acked-by: Jan Beulich <jbeulich@suse.com>
---
Cc: Juergen Gross <jgross@suse.com>
---
 xen/arch/x86/io_apic.c | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/xen/arch/x86/io_apic.c b/xen/arch/x86/io_apic.c
index 37eabc16c9..b9c66acdb3 100644
--- a/xen/arch/x86/io_apic.c
+++ b/xen/arch/x86/io_apic.c
@@ -502,7 +502,7 @@ static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
     struct IO_APIC_route_entry entry;
 
     /* Check delivery_mode to be sure we're not clearing an SMI pin */
-    entry = __ioapic_read_entry(apic, pin, FALSE);
+    entry = __ioapic_read_entry(apic, pin, false);
     if (entry.delivery_mode == dest_SMI)
         return;
 
@@ -512,15 +512,15 @@ static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
      */
     if (!entry.mask) {
         entry.mask = 1;
-        __ioapic_write_entry(apic, pin, FALSE, entry);
+        __ioapic_write_entry(apic, pin, false, entry);
     }
-    entry = __ioapic_read_entry(apic, pin, TRUE);
+    entry = __ioapic_read_entry(apic, pin, true);
 
     if (entry.irr) {
         /* Make sure the trigger mode is set to level. */
         if (!entry.trigger) {
             entry.trigger = 1;
-            __ioapic_write_entry(apic, pin, TRUE, entry);
+            __ioapic_write_entry(apic, pin, true, entry);
         }
         __io_apic_eoi(apic, entry.vector, pin);
     }
@@ -530,9 +530,9 @@ static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
      */
     memset(&entry, 0, sizeof(entry));
     entry.mask = 1;
-    __ioapic_write_entry(apic, pin, TRUE, entry);
+    __ioapic_write_entry(apic, pin, true, entry);
 
-    entry = __ioapic_read_entry(apic, pin, TRUE);
+    entry = __ioapic_read_entry(apic, pin, true);
     if (entry.irr)
         printk(KERN_ERR "IO-APIC%02x-%u: Unable to reset IRR\n",
                IO_APIC_ID(apic), pin);
-- 
2.23.0


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[Xen-devel] [PATCH for-4.13 v2 2/2] x86/ioapic: fix clear_IO_APIC_pin write of raw entries

[Roger Pau Monne]

clear_IO_APIC_pin can be called after the iommu has been enabled, and
using raw reads and writes to modify IO-APIC entries that have been
setup to use interrupt remapping can lead to issues as some of the
fields have different meaning when the IO-APIC entry is setup to point
to an interrupt remapping table entry.

The following ASSERT in AMD IOMMU code triggers afterwards as a result
of the raw changes to IO-APIC entries performed by clear_IO_APIC_pin.

(XEN) [   10.082154] ENABLING IO-APIC IRQs
(XEN) [   10.087789]  -> Using new ACK method
(XEN) [   10.093738] Assertion 'get_rte_index(rte) == offset' failed at iommu_intr.c:328

Fix this by making sure that modifications to entries are performed in
non raw mode.

Reported-by: Sergey Dyasli <sergey.dyasli@citrix.com>
Signed-off-by: Roger Pau Monné <roger.pau@citrix.com>
---
Cc: Juergen Gross <jgross@suse.com>
---
Changes since v1:
 - Do not change all instances of raw reads.
 - Fix commit message
---
 xen/arch/x86/io_apic.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/xen/arch/x86/io_apic.c b/xen/arch/x86/io_apic.c
index b9c66acdb3..732b57995c 100644
--- a/xen/arch/x86/io_apic.c
+++ b/xen/arch/x86/io_apic.c
@@ -519,8 +519,9 @@ static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
     if (entry.irr) {
         /* Make sure the trigger mode is set to level. */
         if (!entry.trigger) {
+            entry = __ioapic_read_entry(apic, pin, false);
             entry.trigger = 1;
-            __ioapic_write_entry(apic, pin, true, entry);
+            __ioapic_write_entry(apic, pin, false, entry);
         }
         __io_apic_eoi(apic, entry.vector, pin);
     }
@@ -530,7 +531,7 @@ static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
      */
     memset(&entry, 0, sizeof(entry));
     entry.mask = 1;
-    __ioapic_write_entry(apic, pin, true, entry);
+    __ioapic_write_entry(apic, pin, false, entry);
 
     entry = __ioapic_read_entry(apic, pin, true);
     if (entry.irr)
-- 
2.23.0


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Re: [Xen-devel] [PATCH for-4.13 v2 2/2] x86/ioapic: fix clear_IO_APIC_pin write of raw entries

[Jan Beulich]

On 10.11.2019 10:25, Roger Pau Monne wrote:
> clear_IO_APIC_pin can be called after the iommu has been enabled, and
> using raw reads and writes to modify IO-APIC entries that have been
> setup to use interrupt remapping can lead to issues as some of the
> fields have different meaning when the IO-APIC entry is setup to point
> to an interrupt remapping table entry.
> 
> The following ASSERT in AMD IOMMU code triggers afterwards as a result
> of the raw changes to IO-APIC entries performed by clear_IO_APIC_pin.
> 
> (XEN) [   10.082154] ENABLING IO-APIC IRQs
> (XEN) [   10.087789]  -> Using new ACK method
> (XEN) [   10.093738] Assertion 'get_rte_index(rte) == offset' failed at iommu_intr.c:328
> 
> Fix this by making sure that modifications to entries are performed in
> non raw mode.

... when fields are affected which may either have changed meaning
with interrupt remapping, or which may need mirroring into IRTEs.

> Reported-by: Sergey Dyasli <sergey.dyasli@citrix.com>
> Signed-off-by: Roger Pau Monné <roger.pau@citrix.com>

With the above addition (or something substantially similar)
Reviewed-by: Jan Beulich <jbeulich@suse.com>
Of course the adjustment is easy enough to do while committing.

Jan

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Re: [Xen-devel] [PATCH for-4.13 v2 0/2] x86/ioapic: fix clear_IO_APIC_pin when using interrupt remapping

[Jürgen Groß]

On 10.11.19 10:25, Roger Pau Monne wrote:
> Hello,
> 
> Current code in clear_IO_APIC_pin doesn't properly deal with IO-APIC
> entries already configured to point to entries in the iommu interrupt
> remapping table, fix this.
> 
> Roger Pau Monne (2):
>    x86/ioapic: remove usage of TRUE and FALSE in clear_IO_APIC_pin
>    x86/ioapic: fix clear_IO_APIC_pin write of raw entries
> 
>   xen/arch/x86/io_apic.c | 13 +++++++------
>   1 file changed, 7 insertions(+), 6 deletions(-)
> 

For the series:

Release-acked-by: Juergen Gross <jgross@suse.com>


Juergen

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Re: [Xen-devel] [PATCH for-4.13 v2 2/2] x86/ioapic: fix clear_IO_APIC_pin write of raw entries

[Roger Pau Monné]

On Mon, Nov 11, 2019 at 10:56:21AM +0100, Jan Beulich wrote:
> On 10.11.2019 10:25, Roger Pau Monne wrote:
> > clear_IO_APIC_pin can be called after the iommu has been enabled, and
> > using raw reads and writes to modify IO-APIC entries that have been
> > setup to use interrupt remapping can lead to issues as some of the
> > fields have different meaning when the IO-APIC entry is setup to point
> > to an interrupt remapping table entry.
> > 
> > The following ASSERT in AMD IOMMU code triggers afterwards as a result
> > of the raw changes to IO-APIC entries performed by clear_IO_APIC_pin.
> > 
> > (XEN) [   10.082154] ENABLING IO-APIC IRQs
> > (XEN) [   10.087789]  -> Using new ACK method
> > (XEN) [   10.093738] Assertion 'get_rte_index(rte) == offset' failed at iommu_intr.c:328
> > 
> > Fix this by making sure that modifications to entries are performed in
> > non raw mode.
> 
> ... when fields are affected which may either have changed meaning
> with interrupt remapping, or which may need mirroring into IRTEs.
> 
> > Reported-by: Sergey Dyasli <sergey.dyasli@citrix.com>
> > Signed-off-by: Roger Pau Monné <roger.pau@citrix.com>
> 
> With the above addition (or something substantially similar)
> Reviewed-by: Jan Beulich <jbeulich@suse.com>
> Of course the adjustment is easy enough to do while committing.

The adjustment LGTM, please do it at commit time unless there's
something else that requires a resend of the series.

Thanks, Roger.

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