From: Jan Beulich <jbeulich@suse.com>
To: Igor Druzhinin <igor.druzhinin@citrix.com>
Cc: andrew.cooper3@citrix.com, roger.pau@citrix.com, wl@xen.org,
jun.nakajima@intel.com, kevin.tian@intel.com,
xen-devel@lists.xenproject.org
Subject: Re: [PATCH v4 1/2] x86/vtx: add LBR_SELECT to the list of LBR MSRs
Date: Wed, 14 Apr 2021 13:41:32 +0200 [thread overview]
Message-ID: <871c259b-487e-4c67-e648-b1aefef55df3@suse.com> (raw)
In-Reply-To: <1618375222-9283-1-git-send-email-igor.druzhinin@citrix.com>
On 14.04.2021 06:40, Igor Druzhinin wrote:
> --- a/xen/arch/x86/hvm/vmx/vmx.c
> +++ b/xen/arch/x86/hvm/vmx/vmx.c
> @@ -2915,14 +2915,16 @@ static const struct lbr_info {
> }, nh_lbr[] = {
> { MSR_IA32_LASTINTFROMIP, 1 },
> { MSR_IA32_LASTINTTOIP, 1 },
> - { MSR_C2_LASTBRANCH_TOS, 1 },
> + { MSR_NHL_LBR_SELECT, 1 },
> + { MSR_NHL_LASTBRANCH_TOS, 1 },
> { MSR_P4_LASTBRANCH_0_FROM_LIP, NUM_MSR_P4_LASTBRANCH_FROM_TO },
> { MSR_P4_LASTBRANCH_0_TO_LIP, NUM_MSR_P4_LASTBRANCH_FROM_TO },
> { 0, 0 }
> }, sk_lbr[] = {
> { MSR_IA32_LASTINTFROMIP, 1 },
> { MSR_IA32_LASTINTTOIP, 1 },
> - { MSR_SKL_LASTBRANCH_TOS, 1 },
> + { MSR_NHL_LBR_SELECT, 1 },
> + { MSR_NHL_LASTBRANCH_TOS, 1 },
> { MSR_SKL_LASTBRANCH_0_FROM_IP, NUM_MSR_SKL_LASTBRANCH },
> { MSR_SKL_LASTBRANCH_0_TO_IP, NUM_MSR_SKL_LASTBRANCH },
> { MSR_SKL_LASTBRANCH_0_INFO, NUM_MSR_SKL_LASTBRANCH },
> @@ -2937,6 +2939,7 @@ static const struct lbr_info {
> }, gm_lbr[] = {
> { MSR_IA32_LASTINTFROMIP, 1 },
> { MSR_IA32_LASTINTTOIP, 1 },
> + { MSR_GM_LBR_SELECT, 1 },
What about Xeon Phi, Silvermont, and Airmont?
> --- a/xen/include/asm-x86/msr-index.h
> +++ b/xen/include/asm-x86/msr-index.h
> @@ -606,14 +606,18 @@
> #define NUM_MSR_C2_LASTBRANCH_FROM_TO 4
> #define NUM_MSR_ATOM_LASTBRANCH_FROM_TO 8
>
> +/* Nehalem (and newer) last-branch recording */
> +#define MSR_NHL_LBR_SELECT 0x000001c8
> +#define MSR_NHL_LASTBRANCH_TOS 0x000001c9
> +
> /* Skylake (and newer) last-branch recording */
> -#define MSR_SKL_LASTBRANCH_TOS 0x000001c9
> #define MSR_SKL_LASTBRANCH_0_FROM_IP 0x00000680
> #define MSR_SKL_LASTBRANCH_0_TO_IP 0x000006c0
> #define MSR_SKL_LASTBRANCH_0_INFO 0x00000dc0
> #define NUM_MSR_SKL_LASTBRANCH 32
>
> /* Goldmont last-branch recording */
> +#define MSR_GM_LBR_SELECT 0x000001c8
> #define MSR_GM_LASTBRANCH_TOS 0x000001c9
Wouldn't it make sense to also re-use the NHL constants, like you
do for Skylake?
Jan
next prev parent reply other threads:[~2021-04-14 11:41 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-04-14 4:40 [PATCH v4 1/2] x86/vtx: add LBR_SELECT to the list of LBR MSRs Igor Druzhinin
2021-04-14 4:40 ` [PATCH v4 2/2] x86/intel: insert Ice Lake-SP and Ice Lake-D model numbers Igor Druzhinin
2021-04-14 12:24 ` Jan Beulich
2021-04-14 11:41 ` Jan Beulich [this message]
2021-04-14 23:13 ` [PATCH v4 1/2] x86/vtx: add LBR_SELECT to the list of LBR MSRs Igor Druzhinin
2021-04-15 9:01 ` Jan Beulich
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