From: Volodymyr Babchuk <Volodymyr_Babchuk@epam.com>
To: Bertrand Marquis <bertrand.marquis@arm.com>
Cc: "xen-devel@lists.xenproject.org" <xen-devel@lists.xenproject.org>,
Stefano Stabellini <sstabellini@kernel.org>,
Julien Grall <julien@xen.org>
Subject: Re: [PATCH v2 4/7] xen/arm: Add handler for ID registers on arm64
Date: Mon, 30 Nov 2020 20:22:06 +0000 [thread overview]
Message-ID: <87pn3u7fyp.fsf@epam.com> (raw)
In-Reply-To: <6db611491b25591829b9408267bd9bd50e266fe2.1606742184.git.bertrand.marquis@arm.com>
Bertrand Marquis writes:
> Add vsysreg emulation for registers trapped when TID3 bit is activated
> in HSR.
> The emulation is returning the value stored in cpuinfo_guest structure
> for most values and the hardware value for registers not stored in the
> structure (those are mostly registers existing only as a provision for
> feature use but who have no definition right now).
I can't see the code that returns values for the registers not stored in
the guest_cpuinfo. Perhaps you need to update the commit description?
> Signed-off-by: Bertrand Marquis <bertrand.marquis@arm.com>
> ---
> Changes in V2: rebase
> ---
> xen/arch/arm/arm64/vsysreg.c | 49 ++++++++++++++++++++++++++++++++++++
> 1 file changed, 49 insertions(+)
>
> diff --git a/xen/arch/arm/arm64/vsysreg.c b/xen/arch/arm/arm64/vsysreg.c
> index 8a85507d9d..970ef51603 100644
> --- a/xen/arch/arm/arm64/vsysreg.c
> +++ b/xen/arch/arm/arm64/vsysreg.c
> @@ -69,6 +69,14 @@ TVM_REG(CONTEXTIDR_EL1)
> break; \
> }
>
> +/* Macro to generate easily case for ID co-processor emulation */
> +#define GENERATE_TID3_INFO(reg,field,offset) \
> + case HSR_SYSREG_##reg: \
> + { \
> + return handle_ro_read_val(regs, regidx, hsr.sysreg.read, hsr, \
> + 1, guest_cpuinfo.field.bits[offset]); \
> + }
> +
> void do_sysreg(struct cpu_user_regs *regs,
> const union hsr hsr)
> {
> @@ -259,6 +267,47 @@ void do_sysreg(struct cpu_user_regs *regs,
> */
> return handle_raz_wi(regs, regidx, hsr.sysreg.read, hsr, 1);
>
> + /*
> + * HCR_EL2.TID3
> + *
> + * This is trapping most Identification registers used by a guest
> + * to identify the processor features
> + */
> + GENERATE_TID3_INFO(ID_PFR0_EL1, pfr32, 0)
> + GENERATE_TID3_INFO(ID_PFR1_EL1, pfr32, 1)
> + GENERATE_TID3_INFO(ID_PFR2_EL1, pfr32, 2)
> + GENERATE_TID3_INFO(ID_DFR0_EL1, dbg32, 0)
> + GENERATE_TID3_INFO(ID_DFR1_EL1, dbg32, 1)
> + GENERATE_TID3_INFO(ID_AFR0_EL1, aux32, 0)
> + GENERATE_TID3_INFO(ID_MMFR0_EL1, mm32, 0)
> + GENERATE_TID3_INFO(ID_MMFR1_EL1, mm32, 1)
> + GENERATE_TID3_INFO(ID_MMFR2_EL1, mm32, 2)
> + GENERATE_TID3_INFO(ID_MMFR3_EL1, mm32, 3)
> + GENERATE_TID3_INFO(ID_MMFR4_EL1, mm32, 4)
> + GENERATE_TID3_INFO(ID_MMFR5_EL1, mm32, 5)
> + GENERATE_TID3_INFO(ID_ISAR0_EL1, isa32, 0)
> + GENERATE_TID3_INFO(ID_ISAR1_EL1, isa32, 1)
> + GENERATE_TID3_INFO(ID_ISAR2_EL1, isa32, 2)
> + GENERATE_TID3_INFO(ID_ISAR3_EL1, isa32, 3)
> + GENERATE_TID3_INFO(ID_ISAR4_EL1, isa32, 4)
> + GENERATE_TID3_INFO(ID_ISAR5_EL1, isa32, 5)
> + GENERATE_TID3_INFO(ID_ISAR6_EL1, isa32, 6)
> + GENERATE_TID3_INFO(MVFR0_EL1, mvfr, 0)
> + GENERATE_TID3_INFO(MVFR1_EL1, mvfr, 1)
> + GENERATE_TID3_INFO(MVFR2_EL1, mvfr, 2)
> + GENERATE_TID3_INFO(ID_AA64PFR0_EL1, pfr64, 0)
> + GENERATE_TID3_INFO(ID_AA64PFR1_EL1, pfr64, 1)
> + GENERATE_TID3_INFO(ID_AA64DFR0_EL1, dbg64, 0)
> + GENERATE_TID3_INFO(ID_AA64DFR1_EL1, dbg64, 1)
> + GENERATE_TID3_INFO(ID_AA64ISAR0_EL1, isa64, 0)
> + GENERATE_TID3_INFO(ID_AA64ISAR1_EL1, isa64, 1)
> + GENERATE_TID3_INFO(ID_AA64MMFR0_EL1, mm64, 0)
> + GENERATE_TID3_INFO(ID_AA64MMFR1_EL1, mm64, 1)
> + GENERATE_TID3_INFO(ID_AA64MMFR2_EL1, mm64, 2)
> + GENERATE_TID3_INFO(ID_AA64AFR0_EL1, aux64, 0)
> + GENERATE_TID3_INFO(ID_AA64AFR1_EL1, aux64, 1)
> + GENERATE_TID3_INFO(ID_AA64ZFR0_EL1, zfr64, 0)
> +
> /*
> * HCR_EL2.TIDCP
> *
--
Volodymyr Babchuk at EPAM
next prev parent reply other threads:[~2020-11-30 20:22 UTC|newest]
Thread overview: 31+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-11-30 14:21 [PATCH v2 0/7] xen/arm: Emulate ID registers Bertrand Marquis
2020-11-30 14:21 ` [PATCH v2 1/7] xen/arm: Add ID registers and complete cpufinfo Bertrand Marquis
2020-11-30 19:55 ` Volodymyr Babchuk
2020-12-04 23:52 ` Stefano Stabellini
2020-12-07 17:35 ` Bertrand Marquis
2020-11-30 14:21 ` [PATCH v2 2/7] xen/arm: Add arm64 ID registers definitions Bertrand Marquis
2020-11-30 20:08 ` Volodymyr Babchuk
2020-12-04 23:54 ` Stefano Stabellini
2020-11-30 14:21 ` [PATCH v2 3/7] xen/arm: create a cpuinfo structure for guest Bertrand Marquis
2020-11-30 20:15 ` Volodymyr Babchuk
2020-12-01 11:41 ` Bertrand Marquis
2020-12-04 23:57 ` Stefano Stabellini
2020-12-07 17:24 ` Bertrand Marquis
2020-11-30 14:21 ` [PATCH v2 4/7] xen/arm: Add handler for ID registers on arm64 Bertrand Marquis
2020-11-30 20:22 ` Volodymyr Babchuk [this message]
2020-12-01 11:42 ` Bertrand Marquis
2020-12-01 11:54 ` Volodymyr Babchuk
2020-12-05 0:19 ` Stefano Stabellini
2020-11-30 14:21 ` [PATCH v2 5/7] xen/arm: Add handler for cp15 ID registers Bertrand Marquis
2020-11-30 20:31 ` Volodymyr Babchuk
2020-12-01 11:46 ` Bertrand Marquis
2020-12-01 12:07 ` Volodymyr Babchuk
2020-12-01 14:21 ` Bertrand Marquis
2020-12-01 16:54 ` Volodymyr Babchuk
2020-12-02 11:12 ` Bertrand Marquis
2020-12-02 11:57 ` Bertrand Marquis
2020-12-05 0:36 ` Stefano Stabellini
2020-11-30 14:21 ` [PATCH v2 6/7] xen/arm: Add CP10 exception support to handle VMFR Bertrand Marquis
2020-11-30 20:39 ` Volodymyr Babchuk
2020-12-01 14:04 ` Bertrand Marquis
2020-11-30 14:21 ` [PATCH v2 7/7] xen/arm: Activate TID3 in HCR_EL2 Bertrand Marquis
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