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d="scan'208";a="14618636" To: Jan Beulich , "xen-devel@lists.xenproject.org" References: <8cf000a6-a8ac-22b6-422d-c11dc8b6454a@suse.com> From: Andrew Cooper Message-ID: <91a633e1-ee5a-7903-b61f-e7905931d3b1@citrix.com> Date: Wed, 25 Mar 2020 14:15:59 +0000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.4.1 MIME-Version: 1.0 In-Reply-To: <8cf000a6-a8ac-22b6-422d-c11dc8b6454a@suse.com> Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Content-Language: en-GB X-ClientProxiedBy: AMSPEX02CAS02.citrite.net (10.69.22.113) To AMSPEX02CL02.citrite.net (10.69.22.126) Subject: Re: [Xen-devel] [PATCH 5/7] x86emul: vendor specific SYSENTER/SYSEXIT behavior in long mode X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Wei Liu , =?UTF-8?Q?Roger_Pau_Monn=c3=a9?= Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" On 24/03/2020 16:28, Jan Beulich wrote: > Intel CPUs permit both insns there while AMD ones don't. > > While at it also > - drop the ring 0 check from SYSENTER handling - neither Intel's nor > AMD's insn pages have any indication of #GP(0) getting raised when > executed from ring 0, and trying it out in practice also confirms > the check shouldn't be there, > - move SYSENTER segment register writing until after the (in principle > able to fail) MSR reads. > > Signed-off-by: Jan Beulich Reviewed-by: Andrew Cooper