From mboxrd@z Thu Jan  1 00:00:00 1970
From: "Xu, Quan" <quan.xu@intel.com>
Subject: Re: [PATCH 1/2] IOMMU/MMU: Adjust top level functions
 for VT-d Device-TLB flush error.
Date: Wed, 30 Mar 2016 02:28:13 +0000
Message-ID: <945CA011AD5F084CBEA3E851C0AB28894B871005@SHSMSX101.ccr.corp.intel.com>
References: <1458197676-60696-1-git-send-email-quan.xu@intel.com>
 <1458197676-60696-2-git-send-email-quan.xu@intel.com>
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 <945CA011AD5F084CBEA3E851C0AB28894B86D176@SHSMSX101.ccr.corp.intel.com>
 <56FA48E302000078000E0B40@prv-mh.provo.novell.com>
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To: Jan Beulich <JBeulich@suse.com>
Cc: "Tian, Kevin" <kevin.tian@intel.com>, "Wu, Feng" <feng.wu@intel.com>, George Dunlap <george.dunlap@eu.citrix.com>, Liu Jinsong <jinsong.liu@alibaba-inc.com>, Dario Faggioli <dario.faggioli@citrix.com>, "xen-devel@lists.xen.org" <xen-devel@lists.xen.org>, "Nakajima,
 Jun" <jun.nakajima@intel.com>, Andrew Cooper <andrew.cooper3@citrix.com>, Keir Fraser <keir@xen.org>
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