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spf=pass smtp.mailfrom=arm.com; dmarc=pass action=none header.from=arm.com; dkim=pass header.d=arm.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=armh.onmicrosoft.com; s=selector2-armh-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=RlbL7v8bpY9VAQR/1LAtAHwMNa+Ynp8uqeKiEXogAXo=; b=9fwFWgk1qfGZ6bMZ+IluecLPu5TZ7HhenWJscrTU8vKlV37YjB7y6NObKK4vAkjHDJRuUD8D+6n7S1+EEWJoFzf3XRB906HFv4dCA4HURkzx68B3M0LnQWTOGpw1pJTy9Z0rakT8i45obZsoY4kEBPSy6+cLZWMpK33+qmE9378= From: Bertrand Marquis To: Julien Grall CC: "xen-devel@lists.xenproject.org" , Julien Grall , Stefano Stabellini , Volodymyr Babchuk Subject: Re: [PATCH for-next v2 2/2] xen/arm64: Place a speculation barrier following an ret instruction Thread-Topic: [PATCH for-next v2 2/2] xen/arm64: Place a speculation barrier following an ret instruction Thread-Index: AQHXGCLUePNZXth41EOpDgjR62uDxqqISyAA Date: Wed, 17 Mar 2021 14:56:25 +0000 Message-ID: References: <20210313160611.18665-1-julien@xen.org> <20210313160611.18665-3-julien@xen.org> In-Reply-To: <20210313160611.18665-3-julien@xen.org> Accept-Language: en-GB, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-mailer: Apple Mail (2.3654.60.0.2.21) Authentication-Results-Original: xen.org; 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X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Mar 2021 14:56:33.9261 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 671c925a-e118-446c-d86d-08d8e954db68 X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d;Ip=[63.35.35.123];Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: VE1EUR03FT012.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM6PR08MB4600 Hi Julien, > On 13 Mar 2021, at 16:06, Julien Grall wrote: >=20 > From: Julien Grall >=20 > Some CPUs can speculate past a RET instruction and potentially perform > speculative accesses to memory before processing the return. >=20 > There is no known gadget available after the RET instruction today. > However some of the registers (such as in check_pending_guest_serror()) > may contain a value provided by the guest. >=20 > In order to harden the code, it would be better to add a speculation > barrier after each RET instruction. The performance impact is meant to > be negligeable as the speculation barrier is not meant to be > architecturally executed. >=20 > Rather than manually inserting a speculation barrier, use a macro > which overrides the mnemonic RET and replace with RET + SB. We need to > use the opcode for RET to prevent any macro recursion. >=20 > This patch is only covering the assembly code. C code would need to be > covered separately using the compiler support. >=20 > This is part of the work to mitigate straight-line speculation. >=20 > Signed-off-by: Julien Grall The macro solution is definitely a great improvement compared to v1 and I c= ould confirm the presence of the sb in the generated code. I also think that the mitigation on arm32/v7 would be messy to do. Shall we mark v7/aarch32 as not security supported ? Apart from this global question (which does not need to be answered in this= serie): Reviewed-by: Bertrand Marquis Cheers Bertrand >=20 > --- >=20 > It is not clear to me whether Armv7 (we don't officially support 32-bit > hypervisor on Armv8) is also affected by straight-line speculation. >=20 > But the mitigation is a lot messier because opcode can be optionally > executed. So this Arm32 is left alone for now. >=20 > Changes in v2: > - Use a macro rather than inserting the speculation barrier > manually > - Remove mitigation for arm32 > --- > xen/arch/arm/arm32/entry.S | 1 + > xen/arch/arm/arm32/lib/lib1funcs.S | 1 + > xen/include/asm-arm/arm64/macros.h | 6 ++++++ > xen/include/asm-arm/macros.h | 18 +++++++++--------- > 4 files changed, 17 insertions(+), 9 deletions(-) >=20 > diff --git a/xen/arch/arm/arm32/entry.S b/xen/arch/arm/arm32/entry.S > index f2f1bc7a3158..d0a066484f13 100644 > --- a/xen/arch/arm/arm32/entry.S > +++ b/xen/arch/arm/arm32/entry.S > @@ -441,6 +441,7 @@ ENTRY(__context_switch) >=20 > add r4, r1, #VCPU_arch_saved_context > ldmia r4, {r4 - sl, fp, sp, pc} /* Load registers and ret= urn */ > + sb >=20 > /* > * Local variables: > diff --git a/xen/arch/arm/arm32/lib/lib1funcs.S b/xen/arch/arm/arm32/lib/= lib1funcs.S > index f1278bd6c139..8c33ffbbcc4c 100644 > --- a/xen/arch/arm/arm32/lib/lib1funcs.S > +++ b/xen/arch/arm/arm32/lib/lib1funcs.S > @@ -382,5 +382,6 @@ UNWIND(.save {lr}) > bl __div0 > mov r0, #0 @ About as wrong as it could be. > ldr pc, [sp], #8 > + sb > UNWIND(.fnend) > ENDPROC(Ldiv0) > diff --git a/xen/include/asm-arm/arm64/macros.h b/xen/include/asm-arm/arm= 64/macros.h > index f981b4f43e84..4614394b3dd5 100644 > --- a/xen/include/asm-arm/arm64/macros.h > +++ b/xen/include/asm-arm/arm64/macros.h > @@ -21,6 +21,12 @@ > ldr \dst, [\dst, \tmp] > .endm >=20 > + .macro ret > + // ret opcode > + .inst 0xd65f03c0 > + sb > + .endm > + > /* > * Register aliases. > */ > diff --git a/xen/include/asm-arm/macros.h b/xen/include/asm-arm/macros.h > index 4833671f4ced..1aa373760f98 100644 > --- a/xen/include/asm-arm/macros.h > +++ b/xen/include/asm-arm/macros.h > @@ -5,6 +5,15 @@ > # error "This file should only be included in assembly file" > #endif >=20 > + /* > + * Speculative barrier > + * XXX: Add support for the 'sb' instruction > + */ > + .macro sb > + dsb nsh > + isb > + .endm > + > #if defined (CONFIG_ARM_32) > # include > #elif defined(CONFIG_ARM_64) > @@ -20,13 +29,4 @@ > .endr > .endm >=20 > - /* > - * Speculative barrier > - * XXX: Add support for the 'sb' instruction > - */ > - .macro sb > - dsb nsh > - isb > - .endm > - > #endif /* __ASM_ARM_MACROS_H */ > --=20 > 2.17.1 >=20