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From: Meng Xu <mengxu@cis.upenn.edu>
To: Dushyant Behl <myselfdushyantbehl@gmail.com>
Cc: Wei Liu <wei.liu2@citrix.com>,
	Stefano Stabellini <stefano.stabellini@eu.citrix.com>,
	Dushyant K Behl <dushyantbehl@in.ibm.com>,
	Xen Devel <xen-devel@lists.xen.org>,
	Julien Grall <julien.grall@arm.com>
Subject: Re: Running Xen on Nvidia Jetson-TK1
Date: Sat, 14 May 2016 14:37:21 -0400	[thread overview]
Message-ID: <CAENZ-+mFD8MqrXB_hgjDQvO1eimsfFFyNBcMqP3fUWerURnz3Q@mail.gmail.com> (raw)
In-Reply-To: <CAHF350+jUGpGzfNqS2iqk9vO4TBUKun9awpqS2ogC9U0vAuX_Q@mail.gmail.com>

Hi Dushyant,

>>> On Thu, Mar 17, 2016 at 8:22 PM, Julien Grall <julien.grall@arm.com>
>>> wrote:
>>>>
>>>> On 14/03/16 14:19, Dushyant Behl wrote:
>>>>>>
>>>>>> Yes, I have enabled these configuration parameters when compiling linux
>>>>>> -
>>>>
>>>>
>>>> The list of options looks good to me. I guess Linux is crashing before
>>>> setting
>>>> up the console. Can you apply the below to Linux and post the log here?
>>>
>>>
>>> I applied your patch to Linux but still there is no output from the
>>> kernel.
>>>
>>> But I have found location of the problem, I have a debugger attached
>>> to the Jetson board
>>> and using that I was able to find out that Linux is failing while
>>> initializing the Tegra timer.
>>>
>>> The call stack at the time of failing is  -
>>>
>>> -   prefetchw (inline)
>>>      arch_spin_lock (inline)
>>>      do_raw_spin_lock_flags (inline)
>>>      __raw_spin_lock_irqssave (inline)
>>>      raw_spin_lock_irq_save (lock = 0xC0B746F0)
>>> -   of_get_parent (node = 0xA00001D3)
>>> -   of_get_address (dev = 0xDBBABC30, index = 0, size = 0xC0A83F30)
>>> -   of_address_to_resource(dev = 0xDBBABC30, index = 0, r = 0xC0A83F50)
>>> -   of_iomap (np = 0xDBBABC30, index = 0)
>>> -   tegra20_init_timer (np = 0xDBBABC30)
>>> -   clocksource_of_init()
>>> -   start_kernel()
>>>
>>> After this Linux jumps to floating point exception handler and then to
>>> undefined instruction and fails.
>>
>>
>> I don't know why Linux is receiving a floating point exception. However,
>> DOM0 must not use the tegra timer as it doesn't support virtualization.
>>
>> You need to ensure that DOM0 will use the arch timer instead. Xen provides
>> some facilities to blacklist a device tree node (see blacklist dev in
>> arm/platforms/tegra.c).
>
> I have blacklisted the tegra20_timer

I guess you blocked the "tegra20-timer" (which uses "-" instead of
"_") right as shown in the following patch? Am I right?

diff --git a/xen/arch/arm/platforms/tegra.c b/xen/arch/arm/platforms/tegra.c

index 5ec9dda..8477ad1 100644

--- a/xen/arch/arm/platforms/tegra.c

+++ b/xen/arch/arm/platforms/tegra.c

@@ -431,6 +431,7 @@ static const struct dt_device_match
tegra_blacklist_dev[] __initconst =

      * UART to dom0, so don't map any of them.

      */

     DT_MATCH_COMPATIBLE("nvidia,tegra20-uart"),

+    DT_MATCH_COMPATIBLE("nvidia,tegra20-timer"),

     { /* sentinel */ },

 };

Thanks and Best Regards,

Meng
-----------
Meng Xu
PhD Student in Computer and Information Science
University of Pennsylvania
http://www.cis.upenn.edu/~mengxu/

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  parent reply	other threads:[~2016-05-14 18:37 UTC|newest]

Thread overview: 31+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-03-08  8:23 Dushyant K Behl
2016-03-09 13:37 ` Wei Liu
2016-03-10  5:08   ` Julien Grall
2016-03-12 14:20     ` Dushyant Behl
2016-03-12 15:27       ` Meng Xu
2016-03-12 20:23         ` Dushyant Behl
2016-03-13  2:10           ` Meng Xu
2016-03-14  9:31             ` Dushyant Behl
2016-03-14 14:12               ` Konrad Rzeszutek Wilk
2016-03-14 14:19                 ` Dushyant Behl
2016-03-17 14:52                   ` Julien Grall
2016-03-18 15:01                     ` Dushyant Behl
2016-03-18 17:23                       ` Julien Grall
2016-03-21 10:12                         ` Dushyant Behl
2016-03-24 11:05                           ` Dushyant Behl
2016-03-29 19:01                             ` Julien Grall
2016-03-29 20:56                               ` Dushyant Behl
2016-04-01 10:04                                 ` Julien Grall
2016-04-07  7:48                                   ` Dushyant Behl
2016-04-08 10:10                                     ` Julien Grall
2016-04-08 12:27                                       ` Ian Campbell
2016-04-14 15:54                                         ` Dushyant Behl
2016-05-14 18:43                                           ` Meng Xu
2016-05-14 19:03                                             ` Dushyant Behl
2016-05-14  2:09                                       ` Meng Xu
2016-05-14 17:36                                         ` Dushyant Behl
2016-05-14 18:34                                           ` Meng Xu
2016-05-14 18:37                           ` Meng Xu [this message]
2016-05-14 18:58                             ` Dushyant Behl
2016-05-12  1:00 ` Meng Xu
2016-05-12  9:19   ` Dushyant Behl

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