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spf=pass smtp.mailfrom=arm.com; dmarc=pass action=none header.from=arm.com; dkim=pass header.d=arm.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=armh.onmicrosoft.com; s=selector2-armh-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=7Cc/cAPggcQ9iLguvdoXkIND+u55kDfmkYFsK+EnMJg=; b=J5z7A/l7mtxaCHj1ouS52IPgwkjgcjEigLXQ9UrNTNNui970XwAb2qBJyMgofRtoRU+uzoTLLkTLsXX9SA93DnIi9P3B5Wq7KKh1+HAV3AlP+QA4xgg3rCmVXFrsIRkJ9dpTPL8ZMyhIigcWSgtN6rAPYm7kApb5ZXD8OLwqWcQ= From: Rahul Singh To: Stefano Stabellini CC: "xen-devel@lists.xenproject.org" , Bertrand Marquis , Julien Grall , Volodymyr Babchuk Subject: Re: [PATCH v2 4/8] xen/arm: Remove support for MSI on SMMUv3 Thread-Topic: [PATCH v2 4/8] xen/arm: Remove support for MSI on SMMUv3 Thread-Index: AQHWxBX8l+Fkiiynvkqd+dcwplqzQKni/UOAgAAB/QCAANIPAA== Date: Wed, 2 Dec 2020 13:12:11 +0000 Message-ID: References: In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: Authentication-Results-Original: kernel.org; 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X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Dec 2020 13:12:51.4850 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 6ae88d13-195d-4402-d9bf-08d896c3f91a X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d;Ip=[63.35.35.123];Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: DB5EUR03FT036.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: VI1PR08MB2926 Hello Stefano, > On 2 Dec 2020, at 12:40 am, Stefano Stabellini w= rote: >=20 > On Tue, 1 Dec 2020, Stefano Stabellini wrote: >> On Thu, 26 Nov 2020, Rahul Singh wrote: >>> XEN does not support MSI on ARM platforms, therefore remove the MSI >>> support from SMMUv3 driver. >>>=20 >>> Signed-off-by: Rahul Singh >>=20 >> I wonder if it makes sense to #ifdef CONFIG_MSI this code instead of >> removing it completely. >=20 > One more thought: could this patch be achieved by reverting > 166bdbd23161160f2abcea70621adba179050bee ? If this patch could be done > by a couple of revert, it would be great to say it in the commit > message. >=20 Ok will add in next version. >=20 >> In the past, we tried to keep the entire file as textually similar to >> the original Linux driver as possible to make it easier to backport >> features and fixes. So, in this case we would probably not even used an >> #ifdef but maybe something like: >>=20 >> if (/* msi_enabled */ 0) >> return; >>=20 >> at the beginning of arm_smmu_setup_msis. >>=20 >>=20 >> However, that strategy didn't actually work very well because backports >> have proven difficult to do anyway. So at that point we might as well at >> least have clean code in Xen and do the changes properly. Main reason to remove the feature/code that is not usable in XEN is to have= a clean code. Regards, Rahul >>=20 >> So that's my reasoning for accepting this patch :-) >>=20 >> Julien, are you happy with this too? >>=20 >>=20 >>> --- >>> xen/drivers/passthrough/arm/smmu-v3.c | 176 +------------------------- >>> 1 file changed, 3 insertions(+), 173 deletions(-) >>>=20 >>> diff --git a/xen/drivers/passthrough/arm/smmu-v3.c b/xen/drivers/passth= rough/arm/smmu-v3.c >>> index cec304e51a..401f7ae006 100644 >>> --- a/xen/drivers/passthrough/arm/smmu-v3.c >>> +++ b/xen/drivers/passthrough/arm/smmu-v3.c >>> @@ -416,31 +416,6 @@ enum pri_resp { >>> PRI_RESP_SUCC =3D 2, >>> }; >>>=20 >>> -enum arm_smmu_msi_index { >>> - EVTQ_MSI_INDEX, >>> - GERROR_MSI_INDEX, >>> - PRIQ_MSI_INDEX, >>> - ARM_SMMU_MAX_MSIS, >>> -}; >>> - >>> -static phys_addr_t arm_smmu_msi_cfg[ARM_SMMU_MAX_MSIS][3] =3D { >>> - [EVTQ_MSI_INDEX] =3D { >>> - ARM_SMMU_EVTQ_IRQ_CFG0, >>> - ARM_SMMU_EVTQ_IRQ_CFG1, >>> - ARM_SMMU_EVTQ_IRQ_CFG2, >>> - }, >>> - [GERROR_MSI_INDEX] =3D { >>> - ARM_SMMU_GERROR_IRQ_CFG0, >>> - ARM_SMMU_GERROR_IRQ_CFG1, >>> - ARM_SMMU_GERROR_IRQ_CFG2, >>> - }, >>> - [PRIQ_MSI_INDEX] =3D { >>> - ARM_SMMU_PRIQ_IRQ_CFG0, >>> - ARM_SMMU_PRIQ_IRQ_CFG1, >>> - ARM_SMMU_PRIQ_IRQ_CFG2, >>> - }, >>> -}; >>> - >>> struct arm_smmu_cmdq_ent { >>> /* Common fields */ >>> u8 opcode; >>> @@ -504,10 +479,6 @@ struct arm_smmu_cmdq_ent { >>> } pri; >>>=20 >>> #define CMDQ_OP_CMD_SYNC 0x46 >>> - struct { >>> - u32 msidata; >>> - u64 msiaddr; >>> - } sync; >>> }; >>> }; >>>=20 >>> @@ -649,12 +620,6 @@ struct arm_smmu_device { >>>=20 >>> struct arm_smmu_strtab_cfg strtab_cfg; >>>=20 >>> - /* Hi16xx adds an extra 32 bits of goodness to its MSI payload */ >>> - union { >>> - u32 sync_count; >>> - u64 padding; >>> - }; >>> - >>> /* IOMMU core code handle */ >>> struct iommu_device iommu; >>> }; >>> @@ -945,20 +910,7 @@ static int arm_smmu_cmdq_build_cmd(u64 *cmd, struc= t arm_smmu_cmdq_ent *ent) >>> cmd[1] |=3D FIELD_PREP(CMDQ_PRI_1_RESP, ent->pri.resp); >>> break; >>> case CMDQ_OP_CMD_SYNC: >>> - if (ent->sync.msiaddr) >>> - cmd[0] |=3D FIELD_PREP(CMDQ_SYNC_0_CS, CMDQ_SYNC_0_CS_IRQ); >>> - else >>> - cmd[0] |=3D FIELD_PREP(CMDQ_SYNC_0_CS, CMDQ_SYNC_0_CS_SEV); >>> - cmd[0] |=3D FIELD_PREP(CMDQ_SYNC_0_MSH, ARM_SMMU_SH_ISH); >>> - cmd[0] |=3D FIELD_PREP(CMDQ_SYNC_0_MSIATTR, ARM_SMMU_MEMATTR_OIWB); >>> - /* >>> - * Commands are written little-endian, but we want the SMMU to >>> - * receive MSIData, and thus write it back to memory, in CPU >>> - * byte order, so big-endian needs an extra byteswap here. >>> - */ >>> - cmd[0] |=3D FIELD_PREP(CMDQ_SYNC_0_MSIDATA, >>> - cpu_to_le32(ent->sync.msidata)); >>> - cmd[1] |=3D ent->sync.msiaddr & CMDQ_SYNC_1_MSIADDR_MASK; >>> + cmd[0] |=3D FIELD_PREP(CMDQ_SYNC_0_CS, CMDQ_SYNC_0_CS_SEV); >>> break; >>> default: >>> return -ENOENT; >>> @@ -1054,50 +1006,6 @@ static void arm_smmu_cmdq_issue_cmd(struct arm_s= mmu_device *smmu, >>> spin_unlock_irqrestore(&smmu->cmdq.lock, flags); >>> } >>>=20 >>> -/* >>> - * The difference between val and sync_idx is bounded by the maximum s= ize of >>> - * a queue at 2^20 entries, so 32 bits is plenty for wrap-safe arithme= tic. >>> - */ >>> -static int __arm_smmu_sync_poll_msi(struct arm_smmu_device *smmu, u32 = sync_idx) >>> -{ >>> - ktime_t timeout; >>> - u32 val; >>> - >>> - timeout =3D ktime_add_us(ktime_get(), ARM_SMMU_CMDQ_SYNC_TIMEOUT_US); >>> - val =3D smp_cond_load_acquire(&smmu->sync_count, >>> - (int)(VAL - sync_idx) >=3D 0 || >>> - !ktime_before(ktime_get(), timeout)); >>> - >>> - return (int)(val - sync_idx) < 0 ? -ETIMEDOUT : 0; >>> -} >>> - >>> -static int __arm_smmu_cmdq_issue_sync_msi(struct arm_smmu_device *smmu= ) >>> -{ >>> - u64 cmd[CMDQ_ENT_DWORDS]; >>> - unsigned long flags; >>> - struct arm_smmu_cmdq_ent ent =3D { >>> - .opcode =3D CMDQ_OP_CMD_SYNC, >>> - .sync =3D { >>> - .msiaddr =3D virt_to_phys(&smmu->sync_count), >>> - }, >>> - }; >>> - >>> - spin_lock_irqsave(&smmu->cmdq.lock, flags); >>> - >>> - /* Piggy-back on the previous command if it's a SYNC */ >>> - if (smmu->prev_cmd_opcode =3D=3D CMDQ_OP_CMD_SYNC) { >>> - ent.sync.msidata =3D smmu->sync_nr; >>> - } else { >>> - ent.sync.msidata =3D ++smmu->sync_nr; >>> - arm_smmu_cmdq_build_cmd(cmd, &ent); >>> - arm_smmu_cmdq_insert_cmd(smmu, cmd); >>> - } >>> - >>> - spin_unlock_irqrestore(&smmu->cmdq.lock, flags); >>> - >>> - return __arm_smmu_sync_poll_msi(smmu, ent.sync.msidata); >>> -} >>> - >>> static int __arm_smmu_cmdq_issue_sync(struct arm_smmu_device *smmu) >>> { >>> u64 cmd[CMDQ_ENT_DWORDS]; >>> @@ -1119,12 +1027,9 @@ static int __arm_smmu_cmdq_issue_sync(struct arm= _smmu_device *smmu) >>> static int arm_smmu_cmdq_issue_sync(struct arm_smmu_device *smmu) >>> { >>> int ret; >>> - bool msi =3D (smmu->features & ARM_SMMU_FEAT_MSI) && >>> - (smmu->features & ARM_SMMU_FEAT_COHERENCY); >>>=20 >>> - ret =3D msi ? __arm_smmu_cmdq_issue_sync_msi(smmu) >>> - : __arm_smmu_cmdq_issue_sync(smmu); >>> - if (ret) >>> + ret =3D __arm_smmu_cmdq_issue_sync(smmu); >>> + if ( ret ) >>> dev_err_ratelimited(smmu->dev, "CMD_SYNC timeout\n"); >>> return ret; >>> } >>> @@ -2898,83 +2803,10 @@ static int arm_smmu_update_gbpa(struct arm_smmu= _device *smmu, u32 set, u32 clr) >>> return ret; >>> } >>>=20 >>> -static void arm_smmu_free_msis(void *data) >>> -{ >>> - struct device *dev =3D data; >>> - platform_msi_domain_free_irqs(dev); >>> -} >>> - >>> -static void arm_smmu_write_msi_msg(struct msi_desc *desc, struct msi_m= sg *msg) >>> -{ >>> - phys_addr_t doorbell; >>> - struct device *dev =3D msi_desc_to_dev(desc); >>> - struct arm_smmu_device *smmu =3D dev_get_drvdata(dev); >>> - phys_addr_t *cfg =3D arm_smmu_msi_cfg[desc->platform.msi_index]; >>> - >>> - doorbell =3D (((u64)msg->address_hi) << 32) | msg->address_lo; >>> - doorbell &=3D MSI_CFG0_ADDR_MASK; >>> - >>> - writeq_relaxed(doorbell, smmu->base + cfg[0]); >>> - writel_relaxed(msg->data, smmu->base + cfg[1]); >>> - writel_relaxed(ARM_SMMU_MEMATTR_DEVICE_nGnRE, smmu->base + cfg[2]); >>> -} >>> - >>> -static void arm_smmu_setup_msis(struct arm_smmu_device *smmu) >>> -{ >>> - struct msi_desc *desc; >>> - int ret, nvec =3D ARM_SMMU_MAX_MSIS; >>> - struct device *dev =3D smmu->dev; >>> - >>> - /* Clear the MSI address regs */ >>> - writeq_relaxed(0, smmu->base + ARM_SMMU_GERROR_IRQ_CFG0); >>> - writeq_relaxed(0, smmu->base + ARM_SMMU_EVTQ_IRQ_CFG0); >>> - >>> - if (smmu->features & ARM_SMMU_FEAT_PRI) >>> - writeq_relaxed(0, smmu->base + ARM_SMMU_PRIQ_IRQ_CFG0); >>> - else >>> - nvec--; >>> - >>> - if (!(smmu->features & ARM_SMMU_FEAT_MSI)) >>> - return; >>> - >>> - if (!dev->msi_domain) { >>> - dev_info(smmu->dev, "msi_domain absent - falling back to wired irqs\= n"); >>> - return; >>> - } >>> - >>> - /* Allocate MSIs for evtq, gerror and priq. Ignore cmdq */ >>> - ret =3D platform_msi_domain_alloc_irqs(dev, nvec, arm_smmu_write_msi_= msg); >>> - if (ret) { >>> - dev_warn(dev, "failed to allocate MSIs - falling back to wired irqs\= n"); >>> - return; >>> - } >>> - >>> - for_each_msi_entry(desc, dev) { >>> - switch (desc->platform.msi_index) { >>> - case EVTQ_MSI_INDEX: >>> - smmu->evtq.q.irq =3D desc->irq; >>> - break; >>> - case GERROR_MSI_INDEX: >>> - smmu->gerr_irq =3D desc->irq; >>> - break; >>> - case PRIQ_MSI_INDEX: >>> - smmu->priq.q.irq =3D desc->irq; >>> - break; >>> - default: /* Unknown */ >>> - continue; >>> - } >>> - } >>> - >>> - /* Add callback to free MSIs on teardown */ >>> - devm_add_action(dev, arm_smmu_free_msis, dev); >>> -} >>> - >>> static void arm_smmu_setup_unique_irqs(struct arm_smmu_device *smmu) >>> { >>> int irq, ret; >>>=20 >>> - arm_smmu_setup_msis(smmu); >>> - >>> /* Request interrupt lines */ >>> irq =3D smmu->evtq.q.irq; >>> if (irq) { >>> @@ -3250,8 +3082,6 @@ static int arm_smmu_device_hw_probe(struct arm_sm= mu_device *smmu) >>> if (reg & IDR0_SEV) >>> smmu->features |=3D ARM_SMMU_FEAT_SEV; >>>=20 >>> - if (reg & IDR0_MSI) >>> - smmu->features |=3D ARM_SMMU_FEAT_MSI; >>>=20 >>> if (reg & IDR0_HYP) >>> smmu->features |=3D ARM_SMMU_FEAT_HYP; >>> --=20 >>> 2.17.1 >>>=20 >>=20