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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?utf-8?B?WnNiQUExdGh6YUN6TThtZkgwZHU2UW9zYnJSK0VEWmZ2ZWFRMWVja0czREtt?= =?utf-8?B?VDRidlZvN3ZJSnNWTHdIa1RRK3V4SFlRYnZBT0UwNEZ3NXJJTlMxcUpKTXFp?= =?utf-8?B?VXg1T3Y1OVY0M3VWeUZIaUVWTHM1KzBQTm03SzJJbU04MXZ0bHhtbXQ1NVBS?= =?utf-8?B?NzNuZTloWjBXK2U2MXpNeVZZelZjOU5oU1FpRFR4enV2YXl5akFNWUNXNVRv?= =?utf-8?B?TzNFMURwdFNnVU5TQnE1L3NiUS9CSU5TYXdEMWtrcmxvaEZvTFBVZjBLV3Qv?= =?utf-8?B?Y0hzcnQrWHVhU2pjMk4rQzJtdlMwbERPRUpZZnV4QmVHR1lsSkhwTTdwbUhh?= =?utf-8?B?MzlWd0l2UFYxYWY1a1lrd0w2OFZjTjYrOUdTUEtLcmMvaktOZk90ZzQvN05Z?= =?utf-8?B?cDNtNXRQemRETVRZZGlZeFJPQ0lMd0M2NklhR2ppK3drektSZXEyTlNwNUx3?= =?utf-8?B?cGRTMmU3aFlnZVhiRU91c0plbkQ1NktaY0QvVGY5ZkVFSHZySnBjWGVzYllC?= =?utf-8?B?ZVNDazFORHdoM2JqazJ4UjBhQlFFZkNzTXZkc0RQYVIwNGJ6NDFxeW5uR0hj?= =?utf-8?B?TGRkSy94NVZSZnZYT0hlckRCaWE2Qy90cHlPVFRpUjh4b2tkMTNCUmQrOG4r?= =?utf-8?B?Q2liQllOenRVbks5Rkw5ZmlNM0JLQ3JWblluOGQxcmNWTXhncHZCMDB6ZUp6?= =?utf-8?B?c3cyLzVQQi94ZllnTkxnK2lVNlorRlZlVklIVERWM1YraklUaFQvdVh0b2ZG?= =?utf-8?B?MG1PTlphUlFlS25zcTl6bWlmeFltd1FkNDNrUmRacS9COEtTeDB3dzVYNTVo?= =?utf-8?B?WEduWHJIN0pPNllUa2E5RENSNEp2ZkJTK2dNaDB1aGIxQWVWZzFqNnl6K1h6?= =?utf-8?B?Smh0K3g1Qmw2Sm92SXQrRzg0amp5UVBEcURPdzZyRHhpSlBtTXpkL291SElG?= =?utf-8?B?elE0elVvUWt1VjJJNUdTaTFVd0hOYXpLOGlQYlZUY1YxTGo1Z2JMV0NjY1ZF?= =?utf-8?B?Z3g0cERSSkhZN3MzQjVuQW5ma1dLeHdkODJudXdEck5MWjJKRUtNMElYQ0hv?= =?utf-8?B?R29lbVNELys2SmZHRUIvNHo0NW9rOUxKbG1VL1BoTGxsMFZWQTBxVEZSMjFp?= =?utf-8?B?MmJ0bzVsYURkZ09lb3IzaUNBME5naytuSktkbTF1elRadUVJZjQreXd4NzRT?= =?utf-8?B?azFKWkloQmxrckhiN2x5dFYrM1BBRzA2TEM5QU9iUzByazlIS2RJeW1vRlpR?= =?utf-8?B?eThOWTY3bVc2azhTOEpxOGtjQ2FEL2pOMzVYUGg1YVJORmkwMTJFamRXaEY1?= =?utf-8?B?SFB6Tk4zQmJtVXNWTUdLR0QrNHdMK09zWEpZZFNFOS9uQU5GVWVSYnVreU1o?= =?utf-8?B?ZzM1NDlkZ2Vnamk0TUFtQmUySzlhdjY5VTBLWC9ZVy9uWkZpT1ErZjN2YlBr?= =?utf-8?B?eTZHVEdPeWhudWpIb21TTnY2d0s3UVNqYmJ2UGt1dWwvcGo4UVFXNThYU1dY?= =?utf-8?B?MDVDamM5c3FjZ1M5dHM3S2VQaTVxYUt0eEhEcW40TjE4UjY5VTNMSHN3MWZN?= =?utf-8?B?SldsSStBODVPbXVZZERuRmM4a1BXck83MnV0TlBPMkNFcVJ5UlQrdHFaMGIx?= =?utf-8?B?U0Rqb25WM3hZcUpaY1B3MkpOV3gxd0ZBRXhtRExHMUVXaXFiRkpueE1pUmR5?= =?utf-8?B?MmRDOGZRWnA1QmpGaCsyWFFwelNCdG5hVEJNTzJYQ2dUSitpYUxjWDBTbzFY?= =?utf-8?Q?iVeFc1oDxKw97q0AiMwP/GhmBNE0kZfT7vqta+v?= X-MS-Exchange-CrossTenant-Network-Message-Id: d3b0e143-b1bb-45c9-ff11-08d98cd4c6e7 X-MS-Exchange-CrossTenant-AuthSource: DS7PR03MB5608.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Oct 2021 16:32:54.9068 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 335836de-42ef-43a2-b145-348c2ee9ca5b X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: I+Xjm/e69YVvJtCHNf0zyqtPAGrg6U9irVYg/gW63OeGlnRmPFD/DioDESyhldjbAZRdMk6iKWYHCl9hvqmtqg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR03MB3369 X-OriginatorOrg: citrix.com On Mon, Oct 11, 2021 at 02:16:19PM +0000, Bertrand Marquis wrote: > Hi Roger, > > > On 11 Oct 2021, at 14:57, Roger Pau Monné wrote: > > > > On Mon, Oct 11, 2021 at 01:40:30PM +0000, Bertrand Marquis wrote: > >> Hi Roger, > >> > >> + Oleksandr to have a better PCI expert then me. > >> > >>> On 11 Oct 2021, at 14:20, Roger Pau Monné wrote: > >>> > >>> On Mon, Oct 11, 2021 at 12:11:04PM +0000, Bertrand Marquis wrote: > >>>> Hi Roger, > >>>> > >>>>> On 11 Oct 2021, at 12:47, Roger Pau Monné wrote: > >>>>> > >>>>> On Wed, Oct 06, 2021 at 06:40:27PM +0100, Rahul Singh wrote: > >>>>>> ARM architecture does not implement I/O ports. Ignore this call on ARM > >>>>>> to avoid the overhead of making a hypercall just for Xen to return > >>>>>> -ENOSYS. > >>>>> > >>>>> What is the cal trace of this function actually on Arm? > >>>>> > >>>>> AFAICT libxl will only call xc_domain_ioport_permission if there are > >>>>> IO ports explicitly defined in the guest configuration, or if any of > >>>>> the BARs of the PCI device is in the IO space, which is not possible > >>>>> on Arm. > >>>> > >>>> PCI devices BARs can be in the IO space as the PCI devices are not > >>>> Arm specific. There is not ioports on arm so to be used those can be > >>>> in some cases remapped and accessed as MMIOs or are not possible > >>>> to use at all. > >>>> > >>>> But the IO space does appear when BARs are listed even on Arm. > >>> > >>> Urg, I wonder whether those devices with IO BARs will work correctly > >>> under Arm then. > >>> > >>> How do you know whether the BAR has been remapped from IO space into > >>> MMIO? > >> > >> We cannot, I think the platform will define if this is the case and where. > >> @oleksandr: I remember that this was discussed during some of our > >> meetings but I have no idea of the details here, can you help ? > >> > >>> > >>> IMO instead of faking a successful return value from > >>> xc_domain_ioport_permission we should avoid the call completely in the > >>> first place, specially if we need to instead issue a call to > >>> xc_domain_iomem_permission. > >> > >> At the end we will never have to issue this because this will never be a matter > >> of “iomem” permission as there would not be any way to cut on something under > >> the page. If this is to be supported one day, it will probably have to be fully emulated > >> to keep the isolation. > > > > So you have a set of memory pages that map accesses from > > MMIO into IO space but it's not possible to isolate specific IO port > > regions as they are all contiguous in the same page(s). > > Exact. > > > > >> Right now on arm you can just make the more simple assumption that ioports are > >> just not supported. > > > > Would it make sense in the future to provide a memory region to guests > > in order to use for IO port accesses, and call > > xc_domain_ioport_permission to set which ports would be allowed? > > Right now we do not plan to support this at all and we will have to > figure this out if we do this one day. > > > > > I think the commit message needs to at least be expanded in order to > > contain the information provided here. It might also be helpful to > > figure out whether we would have to handle IO port accesses in the > > future on Arm, or if it's fine to just ignore them. > > All our investigations and tests have been done without supporting it > without any issues so this is not a critical feature (most devices can > be operated without using the I/O ports). IMO we should let the users know they attempted to use a device with BARs in the IO space, and that those BARs won't be accessible which could make the device not function as expected. Do you think it would be reasonable to attempt the hypercall on Arm also, and in case of error (on Arm) just print a warning message and continue operations as normal? Thanks, Roger.