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From: Corneliu ZUZU <czuzu@bitdefender.com>
To: Julien Grall <julien.grall@arm.com>, xen-devel@lists.xen.org
Cc: Andre Przywara <andre.przywara@arm.com>,
	Stefano Stabellini <sstabellini@kernel.org>,
	Tamas K Lengyel <tamas@tklengyel.com>,
	Razvan Cojocaru <rcojocaru@bitdefender.com>,
	Steve Capper <Steve.Capper@arm.com>
Subject: Re: [PATCH 7/7] vm-event/arm: implement support for control-register write vm-events
Date: Wed, 22 Jun 2016 22:37:24 +0300	[thread overview]
Message-ID: <ade67f43-182d-c4a0-a2d3-25ee4e176826@bitdefender.com> (raw)
In-Reply-To: <bec2a63f-ec61-6fbe-ee47-4869c86018d5@bitdefender.com>

On 6/22/2016 9:39 PM, Corneliu ZUZU wrote:
> On 6/22/2016 8:17 PM, Julien Grall wrote:
>> On 22/06/16 17:35, Corneliu ZUZU wrote:
>>
>>> Julien,
>>
>> Hello Corneliu,
>>
>>> I was trying to implement having HCR stored in arch_domain or arch_vcpu
>>> as suggested above and I'm a bit confused about the code in
>>> p2m_restore_state.
>>> I'm hoping you can provide some feedback on this matter. Here's the
>>> current implementation of the function:
>>>
>>>      void p2m_restore_state(struct vcpu *n)
>>>      {
>>>          register_t hcr;
>>>
>>>          hcr = READ_SYSREG(HCR_EL2);
>>>          WRITE_SYSREG(hcr & ~HCR_VM, HCR_EL2);
>>>          isb();
>>>
>>>          p2m_load_VTTBR(n->domain);
>>>          isb();
>>>
>>>          if ( is_32bit_domain(n->domain) )
>>>              hcr &= ~HCR_RW;
>>>          else
>>>              hcr |= HCR_RW;
>>>
>>>          WRITE_SYSREG(n->arch.sctlr, SCTLR_EL1);
>>>          isb();
>>>
>>>          WRITE_SYSREG(hcr, HCR_EL2);
>>>          isb();
>>>      }
>>>
>>> First of all, I see the HCR_VM bit being unset (=0) but I don't quite
>>> understand why and even more peculiar is the fact that I couldn't find
>>> any place where the bit is set (=1) again.
>>
>> After the first write to HCR_EL2, "hcr" still have the VM bit set as 
>> we only mask it. So the second write will re-set the VM bit.
>>
>
> Ooh..right. Don't know how I missed that, I guess I was too focused in 
> finding a -different- place where HCR was modified.
>
>> I am not sure why the VM bit is unset/set in this function. I am not 
>> able to find a paragraph justifying it in the ARM ARM. I have CCed 
>> some ARM folks to check if I missed something.
>>
>
> An answer to that would be useful. I'm also curious if there's a 
> reason why HCR_RW is set/unset afterwards and not before and why 
> there's an isb() after calling p2m_load_VTTBR if that function already 
> has an isb() @ its end.
>
>>> Secondly, why this order of operations? More specifically, why is
>>> p2m_load_VTTBR done after the HCR_VM bit is unset and before the HCR_RW
>>> bit is set/unset? Can't we write HCR only once here?
>>> And finally, I see the function is called by construct_dom0. The code
>>> there looks like:
>>>
>>>      /*
>>>       * The following loads use the domain's p2m and require current to
>>>       * be a vcpu of the domain, temporarily switch
>>>       */
>>>      saved_current = current;
>>>      p2m_restore_state(v);
>>>      [...]
>>>      /* Now that we are done restore the original p2m and current. */
>>>      set_current(saved_current);
>>>      p2m_restore_state(saved_current);
>>>
>>> I suppose the significant changes p2m_restore_state does for the 
>>> code in
>>> between ("[...]") is setting VTTBR & SCTLR which are used by 
>>> translation
>>> functions such as gvirt_to_maddr (which seems to use PAR_EL1).
>>> What I don't grasp is what effect setting the VTTBR has if 
>>> HCR.HCR_VM is
>>> unset and left unset...
>>
>> HCR.VM is not left unset (see why above).
>>
>> Regards,
>>
>
> Thanks,
> Corneliu.

Julien,

I've also realized that it's a bit complicated to avoid writing HCR from 
2 places.
That's because:
- p2m_restore_state is part of the process of switching to another vCPU 
and the HCR write _must be committed_ here because other components 
depend on that, like address-translation functions
- I want vm_event_vcpu_enter to be called _after_ the switch to the vCPU 
is completed
- I want HCR_TVM to be set in vm_event_vcpu_enter because setting 
necessary traps _for cr vm-events_ to work should be done there (setting 
HCR_TVM bit makes sense to be there and the purpose is to centralize 
operations such as this for code comprehensibility; also, on the X86 
counterpart a similar operation is done for trapping CR3, so it would be 
nice to keep the symmetry)

Would it be such a stretch to have HCR written in 2 places? (the second 
time happens rarely anyway: it's unlikely(..) to have to do the write in 
vm_event_vcpu_enter)

Regards,
Corneliu.

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  reply	other threads:[~2016-06-22 19:37 UTC|newest]

Thread overview: 73+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-06-16 14:04 [PATCH 0/7] vm-event: Implement ARM support for control-register writes Corneliu ZUZU
2016-06-16 14:06 ` [PATCH 1/7] minor (formatting) fixes Corneliu ZUZU
2016-06-16 14:24   ` Jan Beulich
2016-06-16 19:19     ` Corneliu ZUZU
2016-06-17  7:06       ` Jan Beulich
2016-06-17 10:46         ` Corneliu ZUZU
2016-06-16 16:02   ` Tamas K Lengyel
2016-06-17  8:33     ` Corneliu ZUZU
2016-06-17  8:36       ` Razvan Cojocaru
2016-06-17  9:29         ` Andrew Cooper
2016-06-17  9:35           ` Jan Beulich
2016-06-17  9:33         ` Jan Beulich
2016-06-17  9:36           ` Razvan Cojocaru
2016-06-17  9:40             ` Jan Beulich
2016-06-17  9:42               ` Razvan Cojocaru
2016-06-17 19:05           ` Tamas K Lengyel
2016-06-16 14:07 ` [PATCH 2/7] vm-event: VM_EVENT_FLAG_DENY requires VM_EVENT_FLAG_VCPU_PAUSED Corneliu ZUZU
2016-06-16 16:11   ` Tamas K Lengyel
2016-06-17  8:43     ` Corneliu ZUZU
2016-06-21 11:26     ` Corneliu ZUZU
2016-06-21 15:09       ` Tamas K Lengyel
2016-06-22  8:34         ` Corneliu ZUZU
2016-06-16 14:08 ` [PATCH 3/7] vm-event: introduce vm_event_vcpu_enter Corneliu ZUZU
2016-06-16 14:51   ` Jan Beulich
2016-06-16 20:10     ` Corneliu ZUZU
2016-06-16 20:33       ` Razvan Cojocaru
2016-06-17 10:41         ` Corneliu ZUZU
2016-06-17  7:17       ` Jan Beulich
2016-06-17 11:13         ` Corneliu ZUZU
2016-06-17 11:27           ` Jan Beulich
2016-06-17 12:13             ` Corneliu ZUZU
2016-06-16 16:17   ` Tamas K Lengyel
2016-06-17  9:19     ` Corneliu ZUZU
2016-06-17  8:55   ` Julien Grall
2016-06-17 11:40     ` Corneliu ZUZU
2016-06-17 13:22       ` Julien Grall
2016-06-16 14:09 ` [PATCH 4/7] vm-event/x86: use vm_event_vcpu_enter properly Corneliu ZUZU
2016-06-16 15:00   ` Jan Beulich
2016-06-16 20:20     ` Corneliu ZUZU
2016-06-17  7:20       ` Jan Beulich
2016-06-17 11:23         ` Corneliu ZUZU
2016-06-16 16:27   ` Tamas K Lengyel
2016-06-17  9:24     ` Corneliu ZUZU
2016-06-16 14:10 ` [PATCH 5/7] x86: replace monitor_write_data.do_write with enum Corneliu ZUZU
2016-06-16 14:12 ` [PATCH 6/7] vm-event/arm: move hvm_event_cr->common vm_event_monitor_cr Corneliu ZUZU
2016-06-16 15:16   ` Jan Beulich
2016-06-17  8:25     ` Corneliu ZUZU
2016-06-17  8:38       ` Jan Beulich
2016-06-17 11:31         ` Corneliu ZUZU
2016-06-21  7:08       ` Corneliu ZUZU
2016-06-21  7:20         ` Jan Beulich
2016-06-21 15:22           ` Tamas K Lengyel
2016-06-22  6:33             ` Jan Beulich
2016-06-16 16:55   ` Tamas K Lengyel
2016-06-17 10:37     ` Corneliu ZUZU
2016-06-16 14:13 ` [PATCH 7/7] vm-event/arm: implement support for control-register write vm-events Corneliu ZUZU
2016-06-16 14:26   ` Julien Grall
2016-06-16 19:24     ` Corneliu ZUZU
2016-06-16 21:28       ` Julien Grall
2016-06-17 11:46         ` Corneliu ZUZU
2016-06-16 16:49   ` Julien Grall
2016-06-17 10:36     ` Corneliu ZUZU
2016-06-17 13:18       ` Julien Grall
2016-06-22 16:35       ` Corneliu ZUZU
2016-06-22 17:17         ` Julien Grall
2016-06-22 18:39           ` Corneliu ZUZU
2016-06-22 19:37             ` Corneliu ZUZU [this message]
2016-06-22 19:41               ` Julien Grall
2016-06-23  5:31                 ` Corneliu ZUZU
2016-06-23  5:49                   ` Corneliu ZUZU
2016-06-23 11:11                     ` Julien Grall
2016-06-24  9:32                       ` Corneliu ZUZU
2016-06-23 11:00           ` Julien Grall

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