From: Stefano Stabellini <sstabellini@kernel.org>
To: Julien Grall <julien.grall@arm.com>
Cc: sstabellini@kernel.org, wei.chen@arm.com, steve.capper@arm.com,
xen-devel@lists.xen.org, shannon.zhao@linaro.org,
shankerd@codeaurora.org
Subject: Re: [RFC 3/8] xen/arm: gic: split set_irq_properties
Date: Wed, 22 Jun 2016 11:58:57 +0100 (BST) [thread overview]
Message-ID: <alpine.DEB.2.10.1606221158510.2575@sstabellini-ThinkPad-X260> (raw)
In-Reply-To: <1465318123-3090-4-git-send-email-julien.grall@arm.com>
On Tue, 7 Jun 2016, Julien Grall wrote:
> The callback set_irq_properties will configure the GIC for a specific
> IRQ with the type and the priority.
>
> In a follow-up patch, Xen will configure the type and the priority at
> different stage of the routing. So split it in 2 separate callbacks.
>
> At the same time, move the ASSERT to check the validity of the type and
> if the desc->lock is locked in the common code (gic.c). This is because
> the constraint are the same between GICv2 and GICv3, however the driver
> of the latter did not contain any sanity check.
>
> Signed-off-by: Julien Grall <julien.grall@arm.com>
Reviewed-by: Stefano Stabellini <sstabellini@kernel.org>
> xen/arch/arm/gic-v2.c | 19 +++++++++++++------
> xen/arch/arm/gic-v3.c | 15 ++++++++++++---
> xen/arch/arm/gic.c | 23 ++++++++++++++---------
> xen/include/asm-arm/gic.h | 7 ++++---
> 4 files changed, 43 insertions(+), 21 deletions(-)
>
> diff --git a/xen/arch/arm/gic-v2.c b/xen/arch/arm/gic-v2.c
> index 90b07b3..fa2c5a5 100644
> --- a/xen/arch/arm/gic-v2.c
> +++ b/xen/arch/arm/gic-v2.c
> @@ -200,16 +200,12 @@ static unsigned int gicv2_read_irq(void)
> return (readl_gicc(GICC_IAR) & GICC_IA_IRQ);
> }
>
> -static void gicv2_set_irq_properties(struct irq_desc *desc,
> - unsigned int priority)
> +static void gicv2_set_irq_type(struct irq_desc *desc)
> {
> uint32_t cfg, actual, edgebit;
> unsigned int irq = desc->irq;
> unsigned int type = desc->arch.type;
>
> - ASSERT(type != IRQ_TYPE_INVALID);
> - ASSERT(spin_is_locked(&desc->lock));
> -
> spin_lock(&gicv2.lock);
> /* Set edge / level */
> cfg = readl_gicd(GICD_ICFGR + (irq / 16) * 4);
> @@ -234,6 +230,16 @@ static void gicv2_set_irq_properties(struct irq_desc *desc,
> IRQ_TYPE_LEVEL_HIGH;
> }
>
> + spin_unlock(&gicv2.lock);
> +}
> +
> +static void gicv2_set_irq_priority(struct irq_desc *desc,
> + unsigned int priority)
> +{
> + unsigned int irq = desc->irq;
> +
> + spin_lock(&gicv2.lock);
> +
> /* Set priority */
> writeb_gicd(priority, GICD_IPRIORITYR + irq);
>
> @@ -916,7 +922,8 @@ const static struct gic_hw_operations gicv2_ops = {
> .eoi_irq = gicv2_eoi_irq,
> .deactivate_irq = gicv2_dir_irq,
> .read_irq = gicv2_read_irq,
> - .set_irq_properties = gicv2_set_irq_properties,
> + .set_irq_type = gicv2_set_irq_type,
> + .set_irq_priority = gicv2_set_irq_priority,
> .send_SGI = gicv2_send_SGI,
> .disable_interface = gicv2_disable_interface,
> .update_lr = gicv2_update_lr,
> diff --git a/xen/arch/arm/gic-v3.c b/xen/arch/arm/gic-v3.c
> index c936c8a..c25fe50 100644
> --- a/xen/arch/arm/gic-v3.c
> +++ b/xen/arch/arm/gic-v3.c
> @@ -471,8 +471,7 @@ static inline uint64_t gicv3_mpidr_to_affinity(int cpu)
> MPIDR_AFFINITY_LEVEL(mpidr, 0));
> }
>
> -static void gicv3_set_irq_properties(struct irq_desc *desc,
> - unsigned int priority)
> +static void gicv3_set_irq_type(struct irq_desc *desc)
> {
> uint32_t cfg, actual, edgebit;
> void __iomem *base;
> @@ -512,6 +511,15 @@ static void gicv3_set_irq_properties(struct irq_desc *desc,
> IRQ_TYPE_EDGE_RISING :
> IRQ_TYPE_LEVEL_HIGH;
> }
> + spin_unlock(&gicv3.lock);
> +}
> +
> +static void gicv3_set_irq_priority(struct irq_desc *desc,
> + unsigned int priority)
> +{
> + unsigned int irq = desc->irq;
> +
> + spin_lock(&gicv3.lock);
>
> /* Set priority */
> if ( irq < NR_GIC_LOCAL_IRQS )
> @@ -1547,7 +1555,8 @@ static const struct gic_hw_operations gicv3_ops = {
> .eoi_irq = gicv3_eoi_irq,
> .deactivate_irq = gicv3_dir_irq,
> .read_irq = gicv3_read_irq,
> - .set_irq_properties = gicv3_set_irq_properties,
> + .set_irq_type = gicv3_set_irq_type,
> + .set_irq_priority = gicv3_set_irq_priority,
> .send_SGI = gicv3_send_sgi,
> .disable_interface = gicv3_disable_interface,
> .update_lr = gicv3_update_lr,
> diff --git a/xen/arch/arm/gic.c b/xen/arch/arm/gic.c
> index f25381f..0fd7e8c 100644
> --- a/xen/arch/arm/gic.c
> +++ b/xen/arch/arm/gic.c
> @@ -96,14 +96,17 @@ void gic_restore_state(struct vcpu *v)
> gic_restore_pending_irqs(v);
> }
>
> -/*
> - * - desc.lock must be held
> - * - arch.type must be valid (i.e != IRQ_TYPE_INVALID)
> - */
> -static void gic_set_irq_properties(struct irq_desc *desc,
> - unsigned int priority)
> +static void gic_set_irq_type(struct irq_desc *desc)
> +{
> + ASSERT(spin_is_locked(&desc->lock));
> + ASSERT(desc->arch.type != IRQ_TYPE_INVALID);
> +
> + gic_hw_ops->set_irq_type(desc);
> +}
> +
> +static void gic_set_irq_priority(struct irq_desc *desc, unsigned int priority)
> {
> - gic_hw_ops->set_irq_properties(desc, priority);
> + gic_hw_ops->set_irq_priority(desc, priority);
> }
>
> /* Program the GIC to route an interrupt to the host (i.e. Xen)
> @@ -121,7 +124,8 @@ void gic_route_irq_to_xen(struct irq_desc *desc, const cpumask_t *cpu_mask,
>
> desc->handler->set_affinity(desc, cpu_mask);
>
> - gic_set_irq_properties(desc, priority);
> + gic_set_irq_type(desc);
> + gic_set_irq_priority(desc, priority);
> }
>
> /* Program the GIC to route an interrupt to a guest
> @@ -153,7 +157,8 @@ int gic_route_irq_to_guest(struct domain *d, unsigned int virq,
> desc->handler = gic_hw_ops->gic_guest_irq_type;
> set_bit(_IRQ_GUEST, &desc->status);
>
> - gic_set_irq_properties(desc, priority);
> + gic_set_irq_type(desc);
> + gic_set_irq_priority(desc, priority);
>
> p->desc = desc;
> res = 0;
> diff --git a/xen/include/asm-arm/gic.h b/xen/include/asm-arm/gic.h
> index b931f98..ffba469 100644
> --- a/xen/include/asm-arm/gic.h
> +++ b/xen/include/asm-arm/gic.h
> @@ -329,9 +329,10 @@ struct gic_hw_operations {
> void (*deactivate_irq)(struct irq_desc *irqd);
> /* Read IRQ id and Ack */
> unsigned int (*read_irq)(void);
> - /* Set IRQ property */
> - void (*set_irq_properties)(struct irq_desc *desc,
> - unsigned int priority);
> + /* Set IRQ type - type is taken from desc->arch.type */
> + void (*set_irq_type)(struct irq_desc *desc);
> + /* Set IRQ priority */
> + void (*set_irq_priority)(struct irq_desc *desc, unsigned int priority);
> /* Send SGI */
> void (*send_SGI)(enum gic_sgi sgi, enum gic_sgi_mode irqmode,
> const cpumask_t *online_mask);
> --
> 1.9.1
>
_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xen.org
http://lists.xen.org/xen-devel
next prev parent reply other threads:[~2016-06-22 10:58 UTC|newest]
Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-06-07 16:48 [RFC 0/8] xen/arm: acpi: Support SPIs routing Julien Grall
2016-06-07 16:48 ` [RFC 1/8] xen/arm: gic: Consolidate the IRQ affinity set in a single place Julien Grall
2016-06-22 10:46 ` Stefano Stabellini
2016-06-07 16:48 ` [RFC 2/8] xen/arm: gic: Do not configure affinity for guest IRQ during routing Julien Grall
2016-06-22 10:54 ` Stefano Stabellini
2016-06-22 11:19 ` Julien Grall
2016-06-07 16:48 ` [RFC 3/8] xen/arm: gic: split set_irq_properties Julien Grall
2016-06-22 10:58 ` Stefano Stabellini [this message]
2016-06-07 16:48 ` [RFC 4/8] xen/arm: gic: set_type: Pass the type in parameter rather than in desc->arch.type Julien Grall
2016-06-22 11:25 ` Stefano Stabellini
2016-06-07 16:48 ` [RFC 5/8] xen/arm: gic: Document how gic_set_irq_type should be called Julien Grall
2016-06-22 11:00 ` Stefano Stabellini
2016-06-07 16:48 ` [RFC 6/8] Revert "xen/arm: warn the user that we cannot route SPIs to Dom0 on ACPI" Julien Grall
2016-06-22 11:01 ` Stefano Stabellini
2016-06-07 16:48 ` [RFC 7/8] xen/arm: Allow DOM0 to set the irq type when ACPI is inuse Julien Grall
2016-06-22 11:23 ` Stefano Stabellini
2016-06-22 11:46 ` Julien Grall
2016-06-22 11:49 ` Stefano Stabellini
2016-06-07 16:48 ` [RFC 8/8] xen/arm: acpi: route all unused IRQs to DOM0 Julien Grall
2016-06-22 11:44 ` Stefano Stabellini
2016-06-22 12:19 ` Julien Grall
2016-06-07 18:50 ` [RFC 0/8] xen/arm: acpi: Support SPIs routing Shanker Donthineni
2016-06-08 11:48 ` Shanker Donthineni
2016-06-08 11:49 ` Julien Grall
2016-06-08 12:11 ` Shanker Donthineni
2016-06-08 12:34 ` Julien Grall
2016-06-13 11:42 ` Julien Grall
2016-06-13 17:19 ` Shanker Donthineni
2016-06-13 17:20 ` Julien Grall
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=alpine.DEB.2.10.1606221158510.2575@sstabellini-ThinkPad-X260 \
--to=sstabellini@kernel.org \
--cc=julien.grall@arm.com \
--cc=shankerd@codeaurora.org \
--cc=shannon.zhao@linaro.org \
--cc=steve.capper@arm.com \
--cc=wei.chen@arm.com \
--cc=xen-devel@lists.xen.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).