From: Stefano Stabellini <sstabellini@kernel.org>
To: Julien Grall <julien.grall@arm.com>
Cc: xen-devel@lists.xenproject.org, Oleksandr_Tyshchenko@epam.com,
Stefano Stabellini <sstabellini@kernel.org>,
andrii_anisov@epam.com, andre.przywara@arm.com
Subject: Re: [Xen-devel] [PATCH 09/17] xen/arm64: head: Improve coding style and document cpu_init()
Date: Tue, 25 Jun 2019 18:01:11 -0700 (PDT) [thread overview]
Message-ID: <alpine.DEB.2.21.1906251749180.5851@sstabellini-ThinkPad-T480s> (raw)
In-Reply-To: <20190610193215.23704-10-julien.grall@arm.com>
On Mon, 10 Jun 2019, Julien Grall wrote:
> Adjust the coding style used in the comments within cpu_init(). Take the
> opportunity to alter the early print to match the function name.
>
> Lastly, document the behavior and the main registers usage within the
> function.
>
> Signed-off-by: Julien Grall <julien.grall@arm.com>
> ---
> xen/arch/arm/arm64/head.S | 19 ++++++++++++++-----
> 1 file changed, 14 insertions(+), 5 deletions(-)
>
> diff --git a/xen/arch/arm/arm64/head.S b/xen/arch/arm/arm64/head.S
> index 6aa3148192..ee0024173e 100644
> --- a/xen/arch/arm/arm64/head.S
> +++ b/xen/arch/arm/arm64/head.S
> @@ -396,19 +396,26 @@ skip_bss:
> ret
> ENDPROC(zero_bss)
>
> +/*
> + * Initialize the processor for turning the MMU on.
> + *
> + * Clobbers x0 - x4
Shouldn't it be x0 - x3?
The rest looks fine.
> + */
> cpu_init:
> - PRINT("- Setting up control registers -\r\n")
> + PRINT("- Initialize CPU -\r\n")
>
> /* Set up memory attribute type tables */
> ldr x0, =MAIRVAL
> msr mair_el2, x0
>
> - /* Set up TCR_EL2:
> + /*
> + * Set up TCR_EL2:
> * PS -- Based on ID_AA64MMFR0_EL1.PARange
> * Top byte is used
> * PT walks use Inner-Shareable accesses,
> * PT walks are write-back, write-allocate in both cache levels,
> - * 48-bit virtual address space goes through this table. */
> + * 48-bit virtual address space goes through this table.
> + */
> ldr x0, =(TCR_RES1|TCR_SH0_IS|TCR_ORGN0_WBWA|TCR_IRGN0_WBWA|TCR_T0SZ(64-48))
> /* ID_AA64MMFR0_EL1[3:0] (PARange) corresponds to TCR_EL2[18:16] (PS) */
> mrs x1, ID_AA64MMFR0_EL1
> @@ -427,9 +434,11 @@ cpu_init:
> ldr x0, =(HSCTLR_BASE)
> msr SCTLR_EL2, x0
>
> - /* Ensure that any exceptions encountered at EL2
> + /*
> + * Ensure that any exceptions encountered at EL2
> * are handled using the EL2 stack pointer, rather
> - * than SP_EL0. */
> + * than SP_EL0.
> + */
> msr spsel, #1
> ret
> ENDPROC(cpu_init)
> --
> 2.11.0
>
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next prev parent reply other threads:[~2019-06-26 1:01 UTC|newest]
Thread overview: 70+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-06-10 19:31 [Xen-devel] [PATCH 00/17] xen/arm64: Rework head.S to make it more compliant with the Arm Arm Julien Grall
2019-06-10 19:31 ` [Xen-devel] [PATCH 01/17] xen/arm64: head Mark the end of subroutines with ENDPROC Julien Grall
2019-06-25 23:23 ` Stefano Stabellini
2019-06-10 19:32 ` [Xen-devel] [PATCH 02/17] xen/arm64: head: Don't clobber x30/lr in the macro PRINT Julien Grall
2019-06-25 23:35 ` Stefano Stabellini
2019-06-25 23:59 ` Stefano Stabellini
2019-06-26 9:07 ` Julien Grall
2019-06-26 15:27 ` Stefano Stabellini
2019-06-26 15:28 ` Julien Grall
2019-06-26 18:32 ` Stefano Stabellini
2019-06-26 19:24 ` Julien Grall
2019-06-10 19:32 ` [Xen-devel] [PATCH 03/17] xen/arm64: head: Rework UART initialization on boot CPU Julien Grall
2019-06-25 23:49 ` Stefano Stabellini
2019-06-10 19:32 ` [Xen-devel] [PATCH 04/17] xen/arm64: head: Don't "reserve" x24 for the CPUID Julien Grall
2019-06-26 0:01 ` Stefano Stabellini
2019-06-26 9:09 ` Julien Grall
2019-06-10 19:32 ` [Xen-devel] [PATCH 05/17] xen/arm64: head: Introduce print_reg Julien Grall
2019-06-26 0:09 ` Stefano Stabellini
2019-06-26 9:10 ` Julien Grall
2019-07-15 18:46 ` Volodymyr Babchuk
2019-07-16 9:55 ` Julien Grall
2019-06-10 19:32 ` [Xen-devel] [PATCH 06/17] xen/arm64: head: Introduce distinct paths for the boot CPU and secondary CPUs Julien Grall
2019-06-26 1:00 ` Stefano Stabellini
2019-06-26 9:14 ` Julien Grall
2019-06-10 19:32 ` [Xen-devel] [PATCH 07/17] xen/arm64: head: Rework and document check_cpu_mode() Julien Grall
2019-06-26 1:00 ` Stefano Stabellini
2019-06-10 19:32 ` [Xen-devel] [PATCH 08/17] xen/arm64: head: Rework and document zero_bss() Julien Grall
2019-06-26 1:01 ` Stefano Stabellini
2019-06-26 9:16 ` Julien Grall
2019-06-10 19:32 ` [Xen-devel] [PATCH 09/17] xen/arm64: head: Improve coding style and document cpu_init() Julien Grall
2019-06-26 1:01 ` Stefano Stabellini [this message]
2019-06-26 10:34 ` Julien Grall
2019-06-10 19:32 ` [Xen-devel] [PATCH 10/17] xen/arm64: head: Improve coding style and document create_pages_tables() Julien Grall
2019-06-26 1:03 ` Stefano Stabellini
2019-06-26 11:20 ` Julien Grall
2019-06-10 19:32 ` [Xen-devel] [PATCH 11/17] xen/arm64: head: Document enable_mmu() Julien Grall
2019-06-26 1:03 ` Stefano Stabellini
2019-06-26 11:23 ` Julien Grall
2019-06-10 19:32 ` [Xen-devel] [PATCH 12/17] xen/arm64: head: Move assembly switch to the runtime PT in secondary CPUs path Julien Grall
2019-06-26 1:03 ` Stefano Stabellini
2019-06-10 19:32 ` [Xen-devel] [PATCH 13/17] xen/arm64: head: Don't setup the fixmap on secondary CPUs Julien Grall
2019-06-26 18:51 ` Stefano Stabellini
2019-06-26 19:26 ` Julien Grall
2019-06-10 19:32 ` [Xen-devel] [PATCH 14/17] xen/arm64: head: Remove ID map as soon as it is not used Julien Grall
2019-06-26 20:25 ` Stefano Stabellini
2019-06-26 20:39 ` Julien Grall
2019-06-26 20:44 ` Andrew Cooper
2019-06-28 0:36 ` Stefano Stabellini
2019-06-27 18:55 ` Stefano Stabellini
2019-06-27 19:30 ` Julien Grall
2019-07-10 19:39 ` Julien Grall
2019-07-30 17:33 ` Stefano Stabellini
2019-07-30 19:52 ` Julien Grall
2019-07-31 20:40 ` Stefano Stabellini
2019-07-31 21:07 ` Julien Grall
2019-06-10 19:32 ` [Xen-devel] [PATCH 15/17] xen/arm64: head: Rework and document setup_fixmap() Julien Grall
2019-06-26 19:01 ` Stefano Stabellini
2019-06-26 19:30 ` Julien Grall
2019-06-27 9:29 ` Julien Grall
2019-06-27 15:38 ` Stefano Stabellini
2019-06-26 19:02 ` Stefano Stabellini
2019-06-27 9:19 ` Julien Grall
2019-06-10 19:32 ` [Xen-devel] [PATCH 16/17] xen/arm64: head: Rework and document launch() Julien Grall
2019-06-26 19:12 ` Stefano Stabellini
2019-06-26 20:09 ` Julien Grall
2019-06-10 19:32 ` [Xen-devel] [PATCH 17/17] xen/arm64: Zero BSS after the MMU and D-cache is turned on Julien Grall
2019-06-26 19:29 ` Stefano Stabellini
2019-06-26 20:07 ` Julien Grall
2019-06-26 21:08 ` Stefano Stabellini
2019-06-27 11:04 ` Julien Grall
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