Re: [PATCH v2 3/3] x86/ioreq server: Add HVMOP to map guest ram with p2m_ioreq_server to an ioreq server

From: Paul Durrant <Paul.Durrant@citrix.com>
To: "Yu, Zhang" <yu.c.zhang@linux.intel.com>,
	Kevin Tian <kevin.tian@intel.com>,
	Jan Beulich <jbeulich@suse.com>,
	"Nakajima, Jun" <jun.nakajima@intel.com>
Cc: "Keir (Xen.org)" <keir@xen.org>,
	Andrew Cooper <Andrew.Cooper3@citrix.com>,
	"Tim (Xen.org)" <tim@xen.org>,
	George Dunlap <George.Dunlap@citrix.com>,
	"xen-devel@lists.xen.org" <xen-devel@lists.xen.org>,
	"Lv, Zhiyuan" <zhiyuan.lv@intel.com>
Subject: Re: [PATCH v2 3/3] x86/ioreq server: Add HVMOP to map guest ram with p2m_ioreq_server to an ioreq server
Date: Tue, 19 Apr 2016 09:23:33 +0000	[thread overview]
Message-ID: <b282a52fcd4c4a6eb474a9c7db307aaf@AMSPEX02CL03.citrite.net> (raw)
In-Reply-To: <5715F726.5070306@linux.intel.com>

> -----Original Message-----
> From: Yu, Zhang [mailto:yu.c.zhang@linux.intel.com]
> Sent: 19 April 2016 10:15
> To: Kevin Tian; Jan Beulich; Paul Durrant; Nakajima, Jun
> Cc: Keir (Xen.org); George Dunlap; Andrew Cooper; Tim (Xen.org); xen-
> devel@lists.xen.org; Lv, Zhiyuan
> Subject: Re: [Xen-devel] [PATCH v2 3/3] x86/ioreq server: Add HVMOP to
> map guest ram with p2m_ioreq_server to an ioreq server
> 
> 
> 
> On 4/19/2016 12:50 PM, Tian, Kevin wrote:
> >> From: Yu, Zhang [mailto:yu.c.zhang@linux.intel.com]
> >> Sent: Thursday, April 14, 2016 5:57 PM
> >>>>>>> And with all three bits now possibly being clear, aren't we risking
> the
> >>>>>>> entries to be mis-treated as not-present ones?
> >>>>>>
> >>>>>> Hah. You got me. Thanks! :)
> >>>>>> Now I realized it would be difficult if we wanna to emulate the read
> >>>>>> operations for HVM. According to Intel mannual, entry->r is to be
> >>>>>> cleared, so should entry->w if we do not want ept misconfig. And
> >>>>>> with both read and write permissions being forbidden, entry->x can
> be
> >>>>>> set only on processors with EXECUTE_ONLY capability.
> >>>>>> To avoid any entry to be mis-treated as not-present. We have
> several
> >>>>>> solutions:
> >>>>>> a> do not support the read emulation for now - we have no such
> usage
> >>>>>> case;
> >>>>>> b> add the check of p2m_t against p2m_ioreq_server in
> is_epte_present -
> >>>>>> a bit weird to me.
> >>>>>> Which one do you prefer? or any other suggestions?
> >>>>>
> >>>>> That question would also need to be asked to others who had
> >>>>> suggested supporting both. I'd be fine with a, but I also don't view
> >>>>> b as too awkward.
> >>>>
> >>>> According to Intel mannual, an entry is regarded as not present, if
> >>>> bit0:2 is 0. So adding a p2m type check in is_epte_present() means we
> >>>> will change its semantics, if this is acceptable(with no hurt to
> >>>> hypervisor). I'd prefer option b>
> >>>
> >>> Perhaps time for the VMX maintainers to chime in - such a change is
> acceptable
> >>> only if it doesn't result in changed hardware behavior. I can't think of any
> such off
> >>> the top of my head, but this really should be confirmed by the
> maintainers before
> >>> deciding to go such a route.
> >>>
> >>
> >> Thanks, Jan. :)
> >> Jun & Kevin, any suggestions?
> >>
> >
> > I'm a bit worried about this change, since it's a fundamental EPT
> > interface. Can we avoid supporting read emulation now?
> >
> 
> Thanks for your reply, Kevin.
> For XenGT, either waY would be fine. But I do not think changing
> is_epte_present will introduce any bug.
> 
> Paul, do you have any preference?
>

Unless the code is nailed down in the next couple of days then I don't think any implementation is going to make it into 4.7 so I'd prefer to go with the simplest option, and not supporting read emulation makes things a lot simpler.

  Paul

> Yu
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