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From: Jan Beulich <jbeulich@suse.com>
To: Andrew Cooper <andrew.cooper3@citrix.com>
Cc: "xen-devel@lists.xenproject.org" <xen-devel@lists.xenproject.org>,
	"Wei Liu" <wl@xen.org>, "Roger Pau Monné" <roger.pau@citrix.com>
Subject: Re: [PATCH] x86: extend coverage of HLE "bad page" workaround
Date: Tue, 26 May 2020 15:35:05 +0200	[thread overview]
Message-ID: <c27d838e-0331-3cab-25bf-dd16b4645152@suse.com> (raw)
In-Reply-To: <424d1b72-5eb6-f2bc-20fe-e59bacda8dd9@citrix.com>

On 26.05.2020 13:17, Andrew Cooper wrote:
> On 26/05/2020 07:49, Jan Beulich wrote:
>> Respective Core Gen10 processor lines are affected, too.
>>
>> Signed-off-by: Jan Beulich <jbeulich@suse.com>
>>
>> --- a/xen/arch/x86/mm.c
>> +++ b/xen/arch/x86/mm.c
>> @@ -6045,6 +6045,8 @@ const struct platform_bad_page *__init g
>>      case 0x000506e0: /* errata SKL167 / SKW159 */
>>      case 0x000806e0: /* erratum KBL??? */
>>      case 0x000906e0: /* errata KBL??? / KBW114 / CFW103 */
>> +    case 0x000a0650: /* erratum Core Gen10 U/H/S 101 */
>> +    case 0x000a0660: /* erratum Core Gen10 U/H/S 101 */
> 
> This is marred in complexity.
> 
> The enumeration of MSR_TSX_CTRL (from the TAA fix, but architectural
> moving forwards on any TSX-enabled CPU) includes a confirmation that HLE
> no longer exists/works.  This applies to IceLake systems, but possibly
> not their initial release configuration (hence, via a later microcode
> update).
> 
> HLE is also disabled in microcode on all older parts for errata reasons,
> so in practice it doesn't exist anywhere now.
> 
> I think it is safe to drop this workaround, and this does seem a more
> simple option than encoding which microcode turned HLE off (which sadly
> isn't covered by the spec updates, as even when turned off, HLE is still
> functioning according to its spec of "may speed things up, may do
> nothing"), or the interactions with the CPUID hiding capabilities of
> MSR_TSX_CTRL.

I'm afraid I don't fully follow: For one, does what you say imply HLE is
no longer enumerated in CPUID? If so, and if we assume all CPU models
listed have had suitable ucode updates issued, we could indeed drop the
workaround (as taking effect only when HLE is enumerated). But then this
erratum does not have the usual text effectively meaning that an ucode
update is or will be available to address the issue; instead it says
that BIOS or VMM can reserve the respective address range. This -
assuming the alternative you describe is indeed viable - then is surely
a much more intrusive workaround than needed. Which I wouldn't assume
they would suggest in such a case.

Jan


  reply	other threads:[~2020-05-26 13:35 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-05-26  6:49 [PATCH] x86: extend coverage of HLE "bad page" workaround Jan Beulich
2020-05-26 11:17 ` Andrew Cooper
2020-05-26 13:35   ` Jan Beulich [this message]
2020-05-26 15:01     ` Andrew Cooper
2020-05-26 16:40       ` Jan Beulich
2023-03-17 11:39         ` Roger Pau Monné
2023-03-20  9:24           ` Jan Beulich
2023-03-21 14:51             ` Andrew Cooper
2023-03-21 15:59               ` Roger Pau Monné
2023-03-21 16:14                 ` Andrew Cooper
2023-03-21 16:31               ` Jan Beulich
2023-03-21 14:42 ` Roger Pau Monné
2023-03-21 15:51   ` Jan Beulich
2023-03-21 15:58     ` Roger Pau Monné
2023-03-21 16:03       ` Jan Beulich

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