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From: Jan Beulich <jbeulich@suse.com>
To: Andrew Cooper <andrew.cooper3@citrix.com>
Cc: Xen-devel <xen-devel@lists.xenproject.org>,
	"Wei Liu" <wl@xen.org>, "Roger Pau Monné" <roger.pau@citrix.com>
Subject: Re: [PATCH] libx86: Introduce x86_cpu_policy_calculate_compatible() with MSR_ARCH_CAPS handling
Date: Wed, 5 May 2021 17:00:51 +0200	[thread overview]
Message-ID: <d9e03aa4-bbf4-a1ef-bfab-2803e707f498@suse.com> (raw)
In-Reply-To: <8d786331-0d9a-2ec7-0fe5-ba86d4a2547c@citrix.com>

On 05.05.2021 16:50, Andrew Cooper wrote:
> On 05/05/2021 15:48, Jan Beulich wrote:
>> On 05.05.2021 16:29, Andrew Cooper wrote:
>>> Technically, MCXSR_MASK is also a hard blocker to migration, but we
>>> don't even have that data in a consumable form, and we just might be
>>> extremely lucky and discover that it is restricted to non-64-bit CPUs.
>> "it" being what here? The value's presence / absence in an {F,}XSAVE
>> image? Or the precise value of it?
> The precise value of it.

Not sure whether DAZ is new enough, but relatively sure MM isn't.

>  Migrating across the boundary where the
> default changed will cause {F,}RSTOR instructions to #GP.

That's understood. Is there actually anything standing in the way
of treating MXCSR_MASK like yet another feature flag group?


  reply	other threads:[~2021-05-05 15:01 UTC|newest]

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-05-04 21:31 Andrew Cooper
2021-05-05  6:39 ` Jan Beulich
2021-05-05 12:15   ` Andrew Cooper
2021-05-05 12:32     ` Jan Beulich
2021-05-05 10:04 ` Roger Pau Monné
2021-05-05 12:37   ` Andrew Cooper
2021-05-05 13:02     ` Roger Pau Monné
2021-05-05 14:29       ` Andrew Cooper
2021-05-05 14:48         ` Jan Beulich
2021-05-05 14:50           ` Andrew Cooper
2021-05-05 15:00             ` Jan Beulich [this message]
2021-05-05 15:18               ` Andrew Cooper

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