From: Jan Beulich <jbeulich@suse.com>
To: "Tian, Kevin" <kevin.tian@intel.com>
Cc: "xen-devel@lists.xenproject.org" <xen-devel@lists.xenproject.org>,
Roger Pau Monne <roger.pau@citrix.com>,
"Nakajima, Jun" <jun.nakajima@intel.com>, Wei Liu <wl@xen.org>,
Andrew Cooper <andrew.cooper3@citrix.com>
Subject: Re: [Xen-devel] [PATCH v3 7/8] x86/HVM: don't needlessly intercept APERF/MPERF/TSC MSR reads
Date: Mon, 20 Jan 2020 09:32:48 +0100 [thread overview]
Message-ID: <ec3798d3-c63b-8b2b-9c6e-c57741c81b27@suse.com> (raw)
In-Reply-To: <AADFC41AFE54684AB9EE6CBC0274A5D19D739AB2@SHSMSX104.ccr.corp.intel.com>
On 19.01.2020 03:44, Tian, Kevin wrote:
>> From: Jan Beulich <jbeulich@suse.com>
>> Sent: Tuesday, January 7, 2020 12:39 AM
>>
>> If the hardware can handle accesses, we should allow it to do so. This
>> way we can expose EFRO to HVM guests, and "all" that's left for exposing
>> APERF/MPERF is to figure out how to handle writes to these MSRs. (Note
>> that the leaf 6 guest CPUID checks will evaluate to false for now, as
>> recalculate_misc() zaps the entire leaf for now.)
>>
>> For TSC the intercepts are made mirror the RDTSC ones.
>>
>> Signed-off-by: Jan Beulich <jbeulich@suse.com>
>
> Reviewed-by: Kevin Tian <kevin.tian@intel.com>
Thanks. I assume you've seen Andrew's comment, and hence I take it
that the R-b also applies to the adjusted version (not posted yet):
--- a/xen/arch/x86/hvm/vmx/vmcs.c
+++ b/xen/arch/x86/hvm/vmx/vmcs.c
@@ -1140,8 +1140,13 @@ static int construct_vmcs(struct vcpu *v
vmx_clear_msr_intercept(v, MSR_IA32_SYSENTER_CS, VMX_MSR_RW);
vmx_clear_msr_intercept(v, MSR_IA32_SYSENTER_ESP, VMX_MSR_RW);
vmx_clear_msr_intercept(v, MSR_IA32_SYSENTER_EIP, VMX_MSR_RW);
+
+ if ( !(v->arch.hvm.vmx.exec_control & CPU_BASED_RDTSC_EXITING) )
+ vmx_clear_msr_intercept(v, MSR_IA32_TSC, VMX_MSR_R);
+
if ( paging_mode_hap(d) && (!is_iommu_enabled(d) || iommu_snoop) )
vmx_clear_msr_intercept(v, MSR_IA32_CR_PAT, VMX_MSR_RW);
+
if ( (vmexit_ctl & VM_EXIT_CLEAR_BNDCFGS) &&
(vmentry_ctl & VM_ENTRY_LOAD_BNDCFGS) )
vmx_clear_msr_intercept(v, MSR_IA32_BNDCFGS, VMX_MSR_RW);
plus this extra vmx.c hunk:
@@ -1249,7 +1261,12 @@ static void vmx_set_rdtsc_exiting(struct
vmx_vmcs_enter(v);
v->arch.hvm.vmx.exec_control &= ~CPU_BASED_RDTSC_EXITING;
if ( enable )
+ {
v->arch.hvm.vmx.exec_control |= CPU_BASED_RDTSC_EXITING;
+ vmx_set_msr_intercept(v, MSR_IA32_TSC, VMX_MSR_R);
+ }
+ else
+ vmx_clear_msr_intercept(v, MSR_IA32_TSC, VMX_MSR_R);
vmx_update_cpu_exec_control(v);
vmx_vmcs_exit(v);
}
Jan
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next prev parent reply other threads:[~2020-01-20 8:33 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-01-06 16:31 [Xen-devel] [PATCH v3 0/8] x86emul: further work Jan Beulich
2020-01-06 16:34 ` [Xen-devel] [PATCH v3 1/8] x86: determine HAVE_AS_* just once Jan Beulich
2020-01-06 16:41 ` Andrew Cooper
2020-01-06 16:56 ` Jan Beulich
2020-01-20 12:04 ` Roger Pau Monné
2020-01-20 12:36 ` Jan Beulich
2020-01-06 16:35 ` [Xen-devel] [PATCH v3 2/8] x86: move back clang no integrated assembler tests Jan Beulich
2020-01-20 11:37 ` Roger Pau Monné
2020-01-06 16:35 ` [Xen-devel] [PATCH v3 3/8] x86emul: support MOVDIRI insn Jan Beulich
2020-01-06 16:56 ` Andrew Cooper
2020-01-06 17:01 ` Jan Beulich
2020-01-06 16:36 ` [Xen-devel] [PATCH RFC v3 4/8] x86emul: support MOVDIR64B insn Jan Beulich
2020-01-06 19:38 ` Andrew Cooper
2020-01-07 9:01 ` Jan Beulich
2020-01-06 16:37 ` [Xen-devel] [PATCH v3 5/8] x86/HVM: scale MPERF values reported to guests (on AMD) Jan Beulich
2020-01-06 16:37 ` [Xen-devel] [PATCH RFC v3 6/8] x86emul: support RDPRU Jan Beulich
2020-01-06 19:50 ` Andrew Cooper
2020-01-06 16:39 ` [Xen-devel] [PATCH v3 7/8] x86/HVM: don't needlessly intercept APERF/MPERF/TSC MSR reads Jan Beulich
2020-01-19 2:44 ` Tian, Kevin
2020-01-20 8:32 ` Jan Beulich [this message]
2020-01-21 2:45 ` Tian, Kevin
2020-01-06 16:39 ` [Xen-devel] [PATCH RFC v3 8/8] x86emul: support MCOMMIT Jan Beulich
2020-01-06 19:45 ` Andrew Cooper
2020-01-07 9:04 ` Jan Beulich
2020-01-06 16:41 ` [Xen-devel] [PATCH v3 0/8] x86emul: further work Jan Beulich
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